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Evaluating the impact of task migration in multi-processor systems-on-chip
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Authors:
Gabriel Marchesan Almeida
Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), Montpellier, France
Sameer Varyani
Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), Montpellier, France
Rémi Busseuil
Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), Montpellier, France
Gilles Sassatelli
Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), Montpellier, France
Pascal Benoit
Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), Montpellier, France
Lionel Torres
Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), Montpellier, France
Everton Alceu Carara
Pontifical Catholic University of Rio Grande do Sul (PUCRS), Porto Alegre, RS, Brazil
Fernando Gehm Moraes
Pontifical Catholic University of Rio Grande do Sul (PUCRS), Porto Alegre, RS, Brazil
2010 Article
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Published in:
· Proceeding
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Pages 73-78
ACM
New York, NY
, USA
©2010
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ISBN: 978-1-4503-0152-7
doi>
10.1145/1854153.1854174
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Tags:
adaptive
design
distributed memory
experimentation
homogeneous
interconnection architectures
mpsoc
network operating systems
noc
parallel processors
performance
rtos
task migration
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