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Efficient sequential consistency using conditional fences
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Authors:
Changhui Lin
CSE Department, University of California, Riverside, CA, USA
Vijay Nagarajan
School of Informatics, University of Edinburgh, Edinburgh, United Kingdom
Rajiv Gupta
CSE Department, University of California, Riverside, CA, USA
Published in:
· Proceeding
PACT '10
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
ACM
New York, NY
, USA
©2010
table of contents
ISBN: 978-1-4503-0178-7
doi>
10.1145/1854273.1854312
2010 Article
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· Downloads (6 Weeks): 11
· Downloads (12 Months): 200
· Citation Count: 3
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PACT '12
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Tags:
active table
associates
conditional fences
design
experimentation
interprocessor delay
memory consistency
parallel processors
parallel programming
performance
sequential consistency
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