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Countering early evaluation: an approach towards robust dual-rail precharge logic
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Authors:
Shivam Bhasin
Institut TELECOM / TELECOM ParisTech, Paris Cedex, France
Sylvain Guilley
Institut TELECOM / TELECOM ParisTech, Paris Cedex, France
Florent Flament
Institut TELECOM / TELECOM ParisTech, Paris Cedex, France
Nidhal Selmane
Institut TELECOM / TELECOM ParisTech, Paris Cedex, France
Jean-Luc Danger
Institut TELECOM / TELECOM ParisTech, Paris Cedex, France
2010 Article
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Published in:
· Proceeding
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
Article No. 6
ACM
New York, NY
, USA
©2010
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ISBN: 978-1-4503-0078-0
doi>
10.1145/1873548.1873554
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Tags:
design
dpl
early evaluation
mutual information metric
real-time and embedded systems
security
side-channel attack
types and design styles
wddl
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