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A time-predictable dual-core prototype on FPGA
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Authors:
Satya Mohan Raju Gudidevuni
Southern Illinois University Carbondale, IL
Wei Zhang
Southern Illinois University Carbondale, IL
Published in:
· Proceeding
ACM SE '10
Proceedings of the 48th Annual Southeast Regional Conference
Article No. 7
ACM
New York, NY
, USA
©2010
table of contents
ISBN: 978-1-4503-0064-3
doi>
10.1145/1900008.1900020
2010 Article
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Tags:
algorithms
block ram
cache memories
design
lru
performance
priority-1
priority-2
reliability
shared memory
time-predictability
verification
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