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Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation
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Authors:
Etienne Bergeron
Universite de Montreal
Louis-David Perron
Universite de Montreal
Marc Feeley
Universite de Montreal
Jean Pierre David
Ecole Polytechnique de Montreal
2011 Article
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ACM Transactions on Reconfigurable Technology and Systems (TRETS)
TRETS Homepage
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Volume 4 Issue 2, May 2011
Article No. 12
ACM
New York, NY
, USA
table of contents
doi>
10.1145/1968502.1968503
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Tags:
algorithms
bitstream
design
design aids
dynamic configuration
fpga
hardware compilation
jit
performance
reconfigurable computing
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