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A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates
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Authors:
Rahul Singh
Seoul National University, Seoul, South Korea
Jae-Cheol Son
Samsung Electronics, Gyunggi-do, South Korea
Ukrae Cho
Samsung Electronics, Gyunggi-do, South Korea
Gunok Jung
Samsung Electronics, Gyunggi-do, South Korea
Min-Su Kim
Samsung Electronics, Gyunggi-do, South Korea
Hyoungwook Lee
Samsung Electronics, Gyunggi-do, South Korea
Suhwan Kim
Seoul National University, Seoul, South Korea
2011 Article
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Published in:
· Proceeding
GLSVLSI '11
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Pages 127-132
ACM
New York, NY
, USA
©2011
table of contents
ISBN: 978-1-4503-0667-6
doi>
10.1145/1973009.1973036
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Tags:
combinational logic
design
domino logic
dynamic circuits
high speed
logic arrays
low-power design
noise immunity
performance
reliability
switching activity
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