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Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
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Authors:
Feifei Niu
Tsinghua University, Beijing, China
Qiang Zhou
Tsinghua University, Beijing, China
Hailong Yao
Tsinghua University, Beijing, China
Yici Cai
Tsinghua University, Beijing, China
Jianlei Yang
Tsinghua University, Beijing, China
C. N. Sze
IBM Austin Research Laboratory, Austin, TX, USA
2011 Article
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Published in:
· Proceeding
GLSVLSI '11
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Pages 199-204
ACM
New York, NY
, USA
©2011
table of contents
ISBN: 978-1-4503-0667-6
doi>
10.1145/1973009.1973049
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Tags:
algorithms
buffer insertion
clock tree synthesis
computer-aided design
design
obstacle avoidance
performance
skew optimization
slew
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