Scheduling of behavioral VHDL by retiming techniques

Scheduling of behavioral VHDL by retiming techniques

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Authors:	N. Wehn	Siemens AG, ZFE BT SE 52, Otto-Hahn-Ring 6, D-81730 München
	J. Biesenack	Siemens AG, ZFE BT SE 52, Otto-Hahn-Ring 6, D-81730 München
	Peter Duzy	Siemens AG, ZFE BT SE 52, Otto-Hahn-Ring 6, D-81730 München
	T. Langmaier	Siemens AG, ZFE BT SE 52, Otto-Hahn-Ring 6, D-81730 München
	M. Münch	Siemens AG, ZFE BT SE 52, Otto-Hahn-Ring 6, D-81730 München and Institut für Rechnerentwurf und Fehlertolerans, Universität Karlsruhe, D-76128 Karlsruhe
	Michael Pilsl	Siemens AG, ZFE BT SE 52, Otto-Hahn-Ring 6, D-81730 München
	S. Rumler	Siemens AG, ZFE BT SE 52, Otto-Hahn-Ring 6, D-81730 München

	1994 Article
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	· Proceeding
	EURO-DAC '94 Proceedings of the conference on European design automation
	Pages 546-551 IEEE Computer Society Press Los Alamitos, CA, USA ©1994 table of contents ISBN:0-89791-685-9

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Tags: algorithms languages optimization vhdl

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