Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations

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Authors: Wolfgang Ecker Corporate Research and Development, Institut für Datentechnik, Siemens AG - TH Darmstadt, Germany
Manfred Glesner Corporate Research and Development, Institut für Datentechnik, Siemens AG - TH Darmstadt, Germany
Andreas Vombach Corporate Research and Development, Institut für Datentechnik, Siemens AG - TH Darmstadt, Germany
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· Proceeding
EURO-DAC '94 Proceedings of the conference on European design automation
Pages 624-629
IEEE Computer Society Press Los Alamitos, CA, USA ©1994
table of contents ISBN:0-89791-685-9
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations 1994 Article
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