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Cost-effectively offering private buffers in SoCs and CMPs
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Authors:
Zhen Fang
Intel Labs, Hillsboro, OR, USA
Li Zhao
Intel Labs, Hillsboro, OR, USA
Ravishankar R. Iyer
Intel Labs, Hillsboro, OR, USA
Carlos Flores Fajardo
Intel Labs, Guadalajara, Mexico
German Fabila Garcia
Intel, Guadalajara, Mexico
Seung Eun Lee
Seoul National University of Science and Technology, Seoul, South Korea
Bin Li
Intel Labs, Hillsboro, OR, USA
Steve R. King
Intel Labs, Hillsboro, OR, USA
Xiaowei Jiang
Intel Labs, Hillsboro, OR, USA
Srihari Makineni
Intel Labs, Hillsboro, OR, USA
2011 Article
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Published in:
· Proceeding
ICS '11
Proceedings of the international conference on Supercomputing
Pages 275-284
ACM
New York, NY
, USA
©2011
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ISBN: 978-1-4503-0102-2
doi>
10.1145/1995896.1995940
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Tags:
accelerators
cache
design
microprocessor/microcomputer applications
performance
sram
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