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Optimizing explicit data transfers for data parallel applications on the cell architecture
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Authors:
Selma Saidi
Verimag Lab, University of Grenoble and STMicroelectronics Grenoble, France
Pranav Tendulkar
Verimag Lab, University of Grenoble, France
Thierry Lepley
STMicroelectronics Grenoble, France
Oded Maler
CNRS-Verimag Lab, Grenoble, France
2012 Article
Research
Refereed
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ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
TACO Homepage
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Volume 8 Issue 4, January 2012
Article No. 37
ACM
New York, NY
, USA
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doi>
10.1145/2086696.2086716
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Tags:
algorithms
buffering
cell b.e.
data parallelization
design
direct memory access
distributed memories
double buffering
modeling and prediction
performance
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