A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

doi:10.1145/2145694.2145720

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

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Authors:	Sameh Asaad	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	Ralph Bellofatto	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	Bernard Brezzo	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	Chuck Haymes	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	Mohit Kapur	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	Benjamin Parker	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	Thomas Roewer	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	Proshanta Saha	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	Todd Takken	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA
	José Tierno	IBM T.J.Watson Research Center, Yorktown Heights, NY, USA

	2012 Article
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Published in:

	· Proceeding
	FPGA '12 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
	Pages 153-162 ACM New York, NY, USA ©2012 table of contents ISBN: 978-1-4503-1155-7 doi>10.1145/2145694.2145720

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Tags: design fpga-based acceleration general logic emulation multi-core performance performance analysis and design aids verification

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