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OpenCL memory infrastructure for FPGAs (abstract only)
Authors:
S. Alexander Chin
University of Toronto, Toronto, ON, Canada
Paul Chow
University of Toronto, Toronto, ON, Canada
Published in:
· Proceeding
FPGA '12
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Pages 269-270
ACM
New York, NY
, USA
©2012
table of contents
ISBN: 978-1-4503-1155-7
doi>
10.1145/2145694.2145756
2012 Article
Poster
Bibliometrics
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· Citation Count: 0
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FPGA'14
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Tags:
design
dram
experimentation
fpga
memory aggregation
memory coalescing
memory control and access
opencl
performance
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