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A performance and routablity driven router for FPGAs considering path delays
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Authors:
Yuh-sheng Lee
Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.
Allen C.-H. Wu
Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.
Published in:
· Proceeding
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Pages 557-561
ACM
New York, NY
, USA
©1995
table of contents
ISBN:0-89791-725-1
doi>
10.1145/217474.217588
1995 Article
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· Citation Count: 19
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algorithms
design
gate arrays
performance
placement and routing
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