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Statistical Timing and Power Optimization of Architecture and Device for FPGAs
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Authors:
Lerong Cheng
University of California, Los Angeles
Wenyao Xu
University of California, Los Angeles
Fang Gong
University of California, Los Angeles
Yan Lin
University of California, Los Angeles
Ho-Yan Wong
University of California, Los Angeles
Lei He
University of California, Los Angeles
2012 Article
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Refereed
Bibliometrics
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ACM Transactions on Reconfigurable Technology and Systems (TRETS)
TRETS Homepage
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Volume 5 Issue 2, June 2012
Article No. 9
ACM
New York, NY
, USA
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doi>
10.1145/2209285.2209288
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Tags:
design
design aids
fpga architecture
leakage
timing
yield estimation
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