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Optimal code generation for embedded memory non-homogeneous register architectures
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Authors:
Guido Araujo
Department of Electrical Engineering, Princeton University, Princeton, NJ
Sharad Malik
Department of Electrical Engineering, Princeton University, Princeton, NJ
Published in:
· Proceeding
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Pages 36 - 41
ACM
New York, NY
, USA
©1995
table of contents
ISBN:0-89791-771-5
doi>
10.1145/224486.224493
1995 Article
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· Citation Count: 24
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Tags:
[1,/spl infin/] model
algorithms
arithmetic and logic units
code generation
computational complexity
computer architecture
design
embedded memory nonhomogeneous register architectures
expression trees
graph theory
instruction selection
instruction set architecture
instruction set design
instruction sets
microprocessor chips
optimal code generation
optimisation
performance
processor scheduling
register allocation
register transfer graph
scheduling
storage allocation
structural representation
sufficient conditions
theory
tms320c25 processor
trees
verification
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