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On the use of VHDL-based behavioral synthesis for telecom ASIC design
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Authors:
Mark Genoe
Alcatel-Bell, Advanced CAD for VLSI, F.Wellesplein 1, B-2018 Antwerpen, Belgium
Paul Vanoostende
Alcatel-Bell, Advanced CAD for VLSI, F.Wellesplein 1, B-2018 Antwerpen, Belgium
Geert van Wauwe
Alcatel-Bell, Advanced CAD for VLSI, F.Wellesplein 1, B-2018 Antwerpen, Belgium
Published in:
· Proceeding
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Pages 96 - 103
ACM
New York, NY
, USA
©1995
table of contents
ISBN:0-89791-771-5
doi>
10.1145/224486.224514
1995 Article
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Tags:
alcatel-bell
application specific integrated circuits
asic
behavioral synthesis
behavioral synthesis tools
design
design complexities
hardware cad tool
hardware description languages
hardware software codesign
high level synthesis
integrated circuit design
integrated logic circuits
languages
logic synthesis
performance
rtl-synthesizable description
system level design methodology
telecom asic design
telecom system hardware design
telecommunication computing
vhdl
vhdl
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