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Power vs. delay in gate sizing: conflicting objectives?
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Authors:
Sachin S. Sapatnekar
Department of ECE, Iowa State University, Ames, IA
Weitong Chuang
Macronix Semiconductor Co., Science-based Industrial Park, Hsinchu, Taiwan 300
Published in:
· Proceeding
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Computer Society
Washington, DC
, USA
©1995
table of contents
ISBN:0-8186-7213-7
1995 Article
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· Citation Count: 11
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Tags:
circuit cad
circuit optimisation
cmos digital integrated circuits
convex programming
design aids
dynamic power
gate sizing
integrated circuit design
logic cad
logic design
measurement
optimization
optimization problem
performance
power-delay tradeoffs
short-circuit power
theory
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