Design decisions influencing the UltraSPARC's instruction fetch architecture

Design decisions influencing the UltraSPARC's instruction fetch architecture

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Author:

Robert Yung

Sun Microsystems Laboratories, Sun Microsystems Inc.

Published in:

	· Proceeding
	MICRO 29 Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
	Pages 178-190 IEEE Computer Society Washington, DC, USA ©1996 table of contents ISBN:0-8186-7641-8

	1996 Article
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Tags: computer architecture design fast cycle time in-cache prediction instruction fetch architecture instruction fetch unit instruction set design lower cycle-per-instruction microprocessor microprogram design aids performance predictive set-associative cache prefetch and dispatch unit trade-off decisions ultrasparc

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