Driving toward higher I DDQ test quality for sequential circuits: a generalized fault model and its ATPG

Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG

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Authors:	Hisashi Kondo	Kawasaki Steel Corp., LSI Division 1-3 Nakase, Mihama-ku, Chiba 261-01, Japan and Dept. of ECE, University of California, Santa Barbara
	Kwang-Ting Cheng	Electrical and Computer Engineering, University of California, Santa Barbara, CA

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	· Proceeding
	ICCAD '96 Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
	IEEE Computer Society Washington, DC, USA ©1996 table of contents ISBN:0-8186-7597-7

	1997 Article
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Tags: design experimentation iddq, selective iddq, fault model, leakage fault, pseudo stuck-at fault, sequential atpg, vector compaction, test sequential circuits test generation