SIGN IN
SIGN UP
ACV: an arithmetic circuit verifier
Full Text:
PDF
Buy this Article
Authors:
Yirng-An Chen
Carnegie Mellon University, Pittsburgh, PA
Randal E. Bryant
Carnegie Mellon University, Pittsburgh, PA
Published in:
· Proceeding
ICCAD '96
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Pages 361-365
IEEE Computer Society
Washington, DC
, USA
©1996
table of contents
ISBN:0-8186-7597-7
1997 Article
Bibliometrics
· Downloads (6 Weeks): 1
· Downloads (12 Months): 4
· Downloads (cumulative): 113
· Citation Count: 12
Tools and Resources
Buy this Article
TOC Service:
Email
RSS
Save to Binder
Export Formats:
BibTeX
EndNote
ACM Ref
Upcoming Conference:
ICCAD'13
Share:
|
Tags:
algorithms
arithmetic and logic units
design
experimentation
formal verification, arithmetic circuit, binary moment diagram, bmd, hierarchical verification.
hardware description languages
verification
verification
Feedback
|
Switch to
single page view
(no tabs)
**Javascript is not enabled and is required for the "tabbed view" or switch to the
single page view
**
Powered by
The ACM Guide to Computing Literature
All Tags
Export Formats
Save to Binder