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A fine-grained MIMD architecture based upon register channels
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Author:
Rajiv Gupta
Department of Computer Science, University of Pittsburgh, 220 Alumni Hall, Pittsburgh, PA
Published in:
· Proceeding
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Pages 28-37
IEEE Computer Society Press
Los Alamitos, CA
, USA
©1990
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ISBN:0-89791-413-9
1990 Article
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Tags:
aliasing
channels
fine-grained parallelism
instruction scheduling
multiprocessor system
parallelizing compilers
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