SIGN IN
SIGN UP
FPGA routing and routability estimation via Boolean satisfiability
Full Text:
PDF
Buy this Article
Authors:
R. Glenn Wood
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Rob A. Rutenbar
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Published in:
· Proceeding
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Pages 119-125
ACM
New York, NY
, USA
©1997
table of contents
ISBN:0-89791-801-0
doi>
10.1145/258305.258322
1997 Article
Bibliometrics
· Downloads (6 Weeks): 2
· Downloads (12 Months): 8
· Downloads (cumulative): 348
· Citation Count: 15
Tools and Resources
Buy this Article
Request Permissions
TOC Service:
Email
RSS
Save to Binder
Export Formats:
BibTeX
EndNote
ACM Ref
Upcoming Conference:
FPGA'14
Share:
|
Tags:
algorithms
design
experimentation
gate arrays
graph algorithms
placement and routing
Feedback
|
Switch to
single page view
(no tabs)
**Javascript is not enabled and is required for the "tabbed view" or switch to the
single page view
**
Powered by
The ACM Guide to Computing Literature
All Tags
Export Formats
Save to Binder