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A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

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Authors: Weitong Chuang Coordinated Science Laboratory and Dept. of Electrical & Computer Engineering, University of Illinois at Urbana-Champaign
Sachin S. Sapatnekar Department of Electrical Engineering and Computer Engineering, Iowa State University
Ibrahim N. Hajj Coordinated Science Laboratory and Dept. of Electrical & Computer Engineering, University of Illinois at Urbana-Champaign
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· Proceeding
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
IEEE Computer Society Press Los Alamitos, CA, USA ©1993
table of contents ISBN:0-8186-4490-7
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area 1993 Article
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