Effects of delay models on peak power estimation of VLSI sequential circuits

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Authors: Michael S. Hsiao Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ
Elizabeth M. Rudnick Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Janak H. Patel Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Published in:
· Proceeding
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Pages 45-51
IEEE Computer Society Washington, DC, USA ©1997
table of contents ISBN:0-8186-8200-0
Effects of delay models on peak power estimation of VLSI sequential circuits 1997 Article
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