Optimal wire and transistor sizing for circuits with non-tree topology

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Authors: Lieven Vandenberghe Electrical Engineering Dept., University of California, Los Angeles, CA
Stephen Boyd Information Systems Laboratory, Electrical Engineering Dept., Stanford University, Stanford, CA
Abbas El Gamal Information Systems Laboratory, Electrical Engineering Dept., Stanford University, Stanford, CA
Published in:
· Proceeding
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Pages 252-259
IEEE Computer Society Washington, DC, USA ©1997
table of contents ISBN:0-8186-8200-0
Optimal wire and transistor sizing for circuits with non-tree topology 1997 Article
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