A coarse-grained FPGA architecture for high-performance FIR filtering

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Authors: James R. Anderson Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
Siddharth Sheth Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
Kaushik Roy School of Electrical Engineering, Purdue University, West Lafayette, IN
Published in:
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· Proceeding
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Pages 234-244
ACM New York, NY, USA ©1998
table of contents ISBN:0-89791-978-5 doi>10.1145/275107.275143
A coarse-grained FPGA architecture for high-performance FIR filtering Published by ACM 1998 Article
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