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The logic blocks (CLBs) of a lookup table (LUT) based FPGA consist of one or more LUTs, possibly of different sizes. In this paper, we focus on technology mapping for CLBs with several independent LUTs of two different sizes (called ICLBs). The Actel ES6500 family is an example of a class of commercially available ICLBs. Given a tree network with n nodes, the only previously known approach for minimum area tree-based mapping to ICLBs was a heuristic with running time &THgr;(nd+1, where d is the maximum indegree of any node. We give an O(n3) time exact algorithm for mapping a given tree network, an improvement over this heuristic in terms of run time and the solution quality. For general networks, an effective strategy is to break it into trees and combine them. We also give an O(n3) exact algorithm for combining the optimal solutions to these trees, under the condition that LUTs do not go across trees. The method can be extended to solve mapping onto CLBs that can be configured into different ICLBs, (e.g. Xilinx' XC4000E).
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Author image not provided  Madhukar R. Korupolu

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Publication years1997-2016
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Average citations per article14.20
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Author image not provided  K. K. Lee

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Publication years1998-2002
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Author image not provided  D. F. Wong

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Publication years1986-2006
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Downloads (12 Months)514
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top of pageREFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Actel. Actel's Reprogrammable SPGAs. Preliminary Advance Information, Oct. 1996.
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3
A. Fanahi and M. Sarrafzadeh. Complexity of the lookuptable minimization problem for FPGA technology mapping. IEEE Trans. CAD/ICAS, 13( 11):1319-1332, 1994.
4
 
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d He and d Rose. Technology mapping for heterogeneous FPGAs. In Proc. of A CM/SIGDA Intl. Workshop on FP- GAs, 1994.
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Xilinx, XCa000E and XC4000X Series (EX/XL) Field Programmable Gate Arrays. data sheet, drm 1997.
 
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7 Citations

 
 

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The ACM Computing Classification System (CCS rev.2012)

Note: Larger/Darker text within each node indicates a higher relevance of the materials to the taxonomic classification.

top of pagePUBLICATION

Title DAC '98 Proceedings of the 35th annual Design Automation Conference table of contents
Chairmen Basant R. Chawla Lucent Technologies, Warren, NJ
Randal E. Bryant Carnegie Mellon Univ., Pittsburgh, PA
Jan M. Rabaey Univ. of California, Berkeley
Editors M. J. Irwin
Pages 708-711
Publication Date1998-05-01 (yyyy-mm-dd)
Sponsors SIGDA ACM Special Interest Group on Design Automation
IEEE-CS Computer Society
EDAC Electronic Design Automation Consortium
PublisherACM New York, NY, USA ©1998
ISBN: 0-89791-964-5 Order Number: ACM Order Number 477980 doi>10.1145/277044.277222
Conference DACDesign Automation Conference DAC logo
Paper Acceptance Rate 142 of 390 submissions, 36%
Overall Acceptance Rate 3,150 of 10,963 submissions, 29%
Year Submitted Accepted Rate
DAC '84 290 116 40%
DAC '86 300 124 41%
DAC '87 351 138 39%
DAC '88 400 125 31%
DAC '89 465 156 34%
DAC '90 427 125 29%
DAC '94 260 100 38%
DAC '96 377 142 38%
DAC '97 400 139 35%
DAC '98 390 142 36%
DAC '99 451 154 34%
DAC '00 390 142 36%
DAC '01 410 160 39%
DAC '02 491 147 30%
DAC '03 628 152 24%
DAC '04 785 163 21%
DAC '05 735 154 21%
DAC '07 659 152 23%
DAC '08 639 147 23%
DAC '09 684 148 22%
DAC '11 690 156 23%
DAC '12 741 168 23%
Overall 10,963 3,150 29%

APPEARS IN
Hardware Design

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top of pageTable of Contents

Proceedings of the 35th annual Design Automation Conference
Table of Contents
General Chair's Welcome
Page: .03
Executive Committee
Page: .04
Technical Program Committee
Page: .06
1998 Best Paper Award
Page: .09
ACSEE Undergraduate Scholarships
Page: .09
1998 IEEE Fellows
Page: .10
SIGDA Meritorious Service Award
Page: .10
Design Automation Conference Graduate Scholarship Awards
Page: .10
36th Call for Papers
Page: .11
Reviewers
Page: .12
Opening Keynote Address-William J. Spencer
Page: .18
Thursday Keynote Address-George H. Heilmeier
Page: .19
Customers, vendors, and universities (panel): determining the future of EDA together
Thomas Pennino
Page: 1
doi>10.1145/277044.277045
Asynchronous interface specification, analysis and synthesis
Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev
Pages: 2-7
doi>10.1145/277044.277046
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Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed mod ules/agents without common clock. However, the most recent developments in the the ory of asynchronous design in the areas of specifications, ...
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Automatic synthesis of interfaces between incompatible protocols
Roberto Passerone, James A. Rowson, Alberto Sangiovanni-Vincentelli
Pages: 8-13
doi>10.1145/277044.277047
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A t the system level, reusable Intellectual Property (or IP) blo cks can be represented abstractly as blocks that exchange messages. The concrete implementations of these IP blocks m ust exc hange the messages through complex signaling protocols. Interfacing ...
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Automated composition of hardware components
James Smith, Giovanni De Micheli
Pages: 14-19
doi>10.1145/277044.277048
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In order to automate design reuse, methods for composing system components must be developed. The goal of this research is to automate the process of generating interfaces between hardware subsystems. The algorithms presented here can be used ...
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Multilevel integral equation methods for the extraction of substrate coupling parameters in mixed-signal IC's
Mike Chou, Jacob White
Pages: 20-25
doi>10.1145/277044.277049
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The extraction of substrate coupling resistances can be formulated as a first-kind integral equation, which requires only discretization of the two-dimensional contacts. However, the result is a dense matrix problem which is too expensive to store or ...
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Phase noise in oscillators: a unifying theory and numerical methods for characterisation
Alper Demir, Amit Mehrotra, Jaijeet Roychowdhury
Pages: 26-31
doi>10.1145/277044.277050
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Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental ...
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Efficient analog test methodology based on adaptive algorithms
Luigi Carro, Marcelo Negreiros
Pages: 32-37
doi>10.1145/277044.277051
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This papers describes a new, fast and economical methodology totest linear analog circuits based on adaptive algorithms. To theauthors knowledge, this is the first time such technique is used totest analog circuits, allowing complete fault coverage. ...
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General AC constraint transformation for analog ICs
B. G. Arsintescu, E. Charbon, E. Malavasi, U. Choudhury, W. H. Kao
Pages: 38-43
doi>10.1145/277044.277052
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The problem of designing complex analog circuits is attacke dusing a hier archic altop-down, constr aint-driven design methodolo gy. In this methodolo gy, constraints are prop agate dautomatically from high-level specific ationsto physic aldesign ...
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Design methodology used in a single-chip CMOS 900 MHz spread-spectrum wireless transceiver
Jacob Rael, Ahmadreza Rofougaran, Asad Abidi
Pages: 44-49
doi>10.1145/277044.277053
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This paper describes the simulation and layout techniques used and developed in the design of a single-chip CMOS 900 MHz spread-spectrum wireless transceiver:
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A video signal processor for MIMD multiprocessing
Jörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch
Pages: 50-55
doi>10.1145/277044.277054
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The video signal processor AxPe1280V has been developed forimplementation of different video coding applications accordingto standards like ITU-T H.261/H.263, and ISO MPEG-1/2.Itconsists of a RISC processor supplemented by a coprocessor forconvolution-like ...
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Realization of a programmable parallel DSP for high performance image processing applications
Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Bereković, Hanno Lieske, Helge Kloos, Peter Pirsch
Pages: 56-61
doi>10.1145/277044.277055
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Architecture and design of the HiPAR-DSP, a SIMD controlled signalprocessor with parallel data paths, VLIW and novel memory design.The processor architecture is derived from an analysis of thetarget algorithms and specified in VHDL on register transfer ...
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A multiprocessor DSP system using PADDI-2
Roy A. Sutton, Vason P. Srini, Jan M. Rabaey
Pages: 62-65
doi>10.1145/277044.277056
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We have integrated an image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP. The system includes image processing algorithms, a graphical SFG tool, a simulator, routing tools, compilers, hardware configuration and debugging ...
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Design and implementation of the NUMAchine multiprocessor
A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, Z. Zilic
Pages: 66-69
doi>10.1145/277044.277057
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This paper describes the design and implementation of the NUMAchine multiprocessor. As the market for CC-NUMA multiprocessors expands, this research project provides a timely architectural design and cost-effective prototype. The key ...
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Design and specification of embedded systems in Java using successive, formal refinement
James Shin Young, Josh MacDonald, Michael Shilman, Abdallah Tabbara, Paul Hilfinger, A. Richard Newton
Pages: 70-75
doi>10.1145/277044.277058
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Successive, formal refinement is a new approach for specificationof embedded systems using a general-purpose programming language.Systems are formally modeled as Abstractable SynchronousReactive systems, and Java is used as the design inputlanguage. ...
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Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer
Julio Leao da Silva, Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man
Pages: 76-81
doi>10.1145/277044.277059
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Matisse is a design flow intended for developing embedded systems characterize dby tight inter action b etwe encontrol and data-flow behavior, intensive data storage and tr ansfer, dynamic creation of data, and stringent real-time requirements. ...
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Design space exploration algorithm for heterogeneous multi-processor embedded system design
Ireneusz Karkowski, Henk Corporaal
Pages: 82-87
doi>10.1145/277044.277060
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Single-chip multi-processor embedded system becomesnowadays a feasible and very interesting option. What isneeded however is an environment that supports the designerin transforming an algorithmic specification into a suitableparallel implementation. ...
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Modal processes: towards enhanced retargetability through control composition of distributed embedded systems
Pai Chou, Gaetano Borriello
Pages: 88-93
doi>10.1145/277044.277061
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To explore different points in the design space of an embeddedsystem, it is important to be able to compose a designfrom reusable design components, and then map the resultingsystem description onto several possible target architectureswith different ...
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Design methodologies for noise in digital integrated circuits
Kenneth L. Shepard
Pages: 94-99
doi>10.1145/277044.277062
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In this paper, we describe the growing problems of noise in digital integrated circuits and the design tools and techniques used to ensure the noise immunity of digital designs.
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Taming noise in deep submicron digital integrated circuits (panel)
Kenneth Shepard, Takahide Inone / Nagaraj NS
Pages: 100-101
doi>10.1145/277044.277064
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of digital VLSI chips. Are functional failures due to noise really a problem in a ...
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FACT: a framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions
Ganesh Lakshminarayana, Niraj K. Jha
Pages: 102-107
doi>10.1145/277044.277066
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In this paper, we present an algorithm for the application of a general class of transformations to control-flow intensive behavioral descriptions. Our algorithm is based on the observation that incorporation of scheduling information can help guide ...
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Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
Pages: 108-113
doi>10.1145/277044.277067
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Speculative execution refers to the execution of parts of a computation before the execution of the conditional operations that decide whether it needs to be executed. It has been shown to be a promising technique for eliminating performance bottlenecks ...
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The DT-model: high-level synthesis using data transfers
Shantanu Tarafdar, Miriam Leeser
Pages: 114-121
doi>10.1145/277044.277069
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We presen t a new model for formulating the classic HLS sub-problems: scheduling, allocation, and binding. The model is unique in its use of data-transfers as the basic entity in syn thesis. A data transfer represents the movement of one instance of ...
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Rate Optimal VLSI Design from Data Flow Graph
Page: 118

This paper considers the rate optimal VLSI design of a recursivedata flow graph (DFG).Previous research on rateoptimal scheduling is not directly applicable to VLSI design.We propose a technique that inserts buffer registers toallow overlapped rate optimal ...
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Planning for performance
Ralph H. J. M. Otten, Robert K. Brayton
Pages: 122-127
doi>10.1145/277044.277071
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A shift is proposed in the design of VLSI circuits. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing analysis is built into a feedback loop to detect ...
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A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
Amir H. Salek, Jinan Lou, Massoud Pedram
Pages: 128-134
doi>10.1145/277044.277072
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This paper presents an integrated design flowwhich combines floorplanning, technology mapping, andplacement using a dynamic programming algorithm. Theproposed design flow consists of five steps: maximum treesub-structure formation, levelized cluster ...
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Framework encapsulations: a new approach to CAD tool interoperability
Peter R. Sutton, Stephen W. Director
Pages: 134-139
doi>10.1145/277044.277074
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Today's complex leading-edge design processes require the use of multiple CAD tools that operate in multiple frameworks making management of the complete design process difficult. This paper introduces the concept of framework encapsulations: software ...
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A geographically distributed framework for embedded system design and validation
Ken Hines, Gaetano Borriello
Pages: 140-145
doi>10.1145/277044.277075
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The difficulty of emb edded system co-design is increasing rapidly due to the incr easing complexity of individual parts, the variety of parts available and pr essure to use multiple processors to me et performanc e criteria. V alidation tools ...
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WELD—an environment for Web-based electronic design
Francis L. Chan, Mark D. Spiller, A. Richard Newton
Pages: 146-151
doi>10.1145/277044.277077
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Increasing size and geographical separation of design data and teams has created a need for a network-based electronic design environment that is scaleable, adaptable, secure, highly available, and cost effective. In the WELD project we are evaluating ...
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OCCOM: efficient computation of observability-based code coverage metrics for functional verification
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Pages: 152-157
doi>10.1145/277044.277078
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Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important ...
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User defined coverage—a tool supported methodology for design verification
Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv
Pages: 158-163
doi>10.1145/277044.277081
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This paper describes a new coverage methodology developed at IBM's Haifa Research Lab. The main idea behind the methodology is a separation of the coverage model definition from the coverage analysis tool. This enables the user to define the coverage ...
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Enhanced visibility and performance in functional verification by reconstruction
Joshua Marantz
Pages: 164-169
doi>10.1145/277044.277083
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Cycle simulators, in-circuit emulators, and hardware accelerators have made it possible to rapidly model the functionality of large digital designs. But these techniques provide limited visibility of internal design nodes, making debugging hard. Simulators ...
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Virtual chip: making functional models work on real target systems
Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheolo Park, Chong-Min Kyung
Pages: 170-173
doi>10.1145/277044.277084
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As design complexity increases, functional verification becomes a crucial issue to ensure design correctness at an early design stage. Traditional methods for verifying functional designs are based on the HDL simulation, which is becoming the bottleneck ...
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Hardware/software co-design (panel): the next embedded system design challenge
Peter Heller
Pages: 174-175
doi>10.1145/277044.277086
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With the proliferation of consumer electronics, the number of embedded systems is growing dramatically, according to Collett International Inc.'s research. At the same time, embedded systems are growing in size and complexity. Another major trend is ...
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Power optimization of variable voltage core-based systems
Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkonjak, Mani B. Srivastava
Pages: 176-181
doi>10.1145/277044.277088
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The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. We develop the design ...
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Policy optimization for dynamic power management
G. A. Paleologo, L. Benini, A. Bogliolo, G. De Micheli
Pages: 182-187
doi>10.1145/277044.277094
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Dynamic power management schemes (also called policies) can be used to control the power consumption levels of electronic systems, by setting their components in different states, each characterized by a performance level and a power consumption. ...
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A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
Yanbing Li, Jörg Henkel
Pages: 188-193
doi>10.1145/277044.277097
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Embedded system design is one of the most challenging tasks in VLSI CAD because of the vast amount of system parameters to fix and the great variety of constraints to meet. In this paper we focus on the constraint of low energy dissipation, an indispensable ...
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Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability
Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi
Pages: 194-199
doi>10.1145/277044.277098
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The Boolean satisfiability problem lies at the core of several CAD applications, including automatic test pattern generation and logic synthesis. This paper describes and evaluates an approach for accelerating Boolean satisfiability using configurable ...
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Fast exact minimization of BDDs
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
Pages: 200-205
doi>10.1145/277044.277099
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We present a new exact algorithm for finding the optimal variable or deringfor r educ edordered Binary Decision Diagrams (BDDs). The algorithm makes use of a lower bound technique known from VLSI design.Up to now this technique has been use donly ...
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Boolean matching for large libraries
Uwe Hinsberger, Reiner Kolla
Pages: 206-211
doi>10.1145/277044.277100
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Boolean matching tackles the problem whether a subcircuit of a boolean network can be substituted by a cell from a cell library. In previous approaches [7, 10, 8] each pair of a subcircuit and a cell is tested for NPN equivalence. This becomes very expensive ...
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A fast hierarchical algorithm for 3-D capacitance extraction
Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu
Pages: 212-217
doi>10.1145/277044.277101
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We presen t a new algorithm for computing the capacitance of three-dimensional perfect electrical conductors of complex structures. The new algorithm is significantly faster and uses muc h less memory than previous best algorithms, and is kernel independent. The ...
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Boundary element method macromodels for 2-D hierachical capacitance extraction
E. Aykut Dengi, Ronald A. Rohrer
Pages: 218-223
doi>10.1145/277044.277102
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We presen t a new algorithm for computing the capacitance of three-dimensional perfect electrical conductors of complex structures. The new algorithm is significantly faster and uses muc h less memory than previous best algorithms, and is kernel independent. The ...
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Efficient thee-dimensional extraction based on static and full-wave layered Green's functions
Jinsong Zhao, Wayne W. M. Dai, Sharad Kapur, David E. Long
Pages: 224-229
doi>10.1145/277044.277103
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In tegral equation approaches based on layered media Green's functions are often used to extract models of integrated circuit structures. The primary advan tage of these approaches over equiv alen t-sourcebased schemes is the dramatic reduction in problem ...
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Robust Elmore delay models suitable for full chip timing verification of a 600MHz CMOS microprocessor
Nevine Nassif, Madhav P. Desai, Dale H. Hall
Pages: 230-235
doi>10.1145/277044.277104
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In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. ...
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A top-down design environment for developing pipelined datapaths
Robert McGraw, James H. Aylor, Robert H. Klenke
Pages: 236-241
doi>10.1145/277044.277105
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This paper presents a design environment for cycle-based systems, such as microprocessors, that permits modeling of these systems at various levels, from the abstract system level, through the detailed RTL level, to an actual implementation. ...
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Validation of an architectural level power analysis technique
Rita Yu Chen, Robert M. Owens, Mary Jane Irwin, R. S. Bajwa, Raminder S. Bajwa
Pages: 242-245
doi>10.1145/277044.277106
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This paper presents a technique used to do po wer analysis of a real p rocessor at the architectural lev el. The target processor in tegrates a 16-bit DSP an d a 32-bit RISC on a single c hip. O ur po wer estimator pro vides po wer consumption data of ...
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Design methodology of a 200MHz superscalar microprocessor: SH-4
Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura
Pages: 246-249
doi>10.1145/277044.277108
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A new design methodology focusing on high speed operation and short design time is described for the SH-4 200MHz superscalar microprocessor. Random test generation, logic emulation, and formal verification are applied to logic verification for shortening ...
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How much analog does a designer need to know for successful mixed-signal design? (panel)
Stephan Ohr
Page: 250
doi>10.1145/277044.277112
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Hierarchical algorithms for assessing probabilistic constraints on system performance
G. de Veciana, M. Jacome, J.-H. Guo
Pages: 251-256
doi>10.1145/277044.277113
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We propose an algorithm for assessing probabilistic performance constraints for systems including components with uncertain delays. We make a case for designing systems based on a probabilistic relaxation of performance constraints, as this has the potential ...
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A tool for performance estimation of networked embedded end-systems
Asawaree Kalavade, Pratyush Moghé
Pages: 257-262
doi>10.1145/277044.277116
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Networked embedded systems are expected to support adaptive streaming audio/video applications with soft real-time constraints. These systems can be designed in a cost efficient manner only if their architecture exploits the “leads” ...
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Rate derivation and its applications to reactive, real-time embedded systems
Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta
Pages: 263-268
doi>10.1145/277044.277118
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An embedded system (the system) continuously interacts with its environment under strict timing constraints, called the external constraints, and it is important to know how these external constraints translate to time budgets, called the internal constraints, ...
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Generic global placement and floorplanning
Hans Eisenmann, Frank M. Johannes
Pages: 269-274
doi>10.1145/277044.277119
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We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use additional forces to reduce cell overlaps and to consider the placement area. Compared to existing approaches, the main advantage ...
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Congestion driven quadratic placement
Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah
Pages: 275-278
doi>10.1145/277044.277121
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This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring congestion. The algorithm uses an A* router and line-probe heuristics on region-based routing graphs to compute routing cost. The ...
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Potential-NRG: placement with incomplete data
Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh
Pages: 279-282
doi>10.1145/277044.277123
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T raditional placement problems are studied under a fully specified cell library and a complete netlist. Ho w ev er, in the first, e.g., 2 years of a 2-3 year microprocessor design cycle, the detailed netlist is una vailable. F or area and performance ...
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Performance-driven multi-FPGA partitioning using functional clustering and replication
Wen-Jong Fang, Allen C.-H. Wu
Pages: 283-286
doi>10.1145/277044.277125
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This paper presents a new performance-driven partitioning method for multi-FPGA designs. The proposed method consists of three steps: (1) functional-cluster formation, (2) slack computation, and (3) set-covering-based partitioning with functional ...
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Multi-pad power/ground network design for uniform distribution of ground bounce
Jaewon Oh, Massoud Pedram
Pages: 287-290
doi>10.1145/277044.277128
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This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the ground bounce, but to distribute it more evenly among the pads while the ...
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Layout extraction and verification methodology CMOS I/O circuits
Tong Li, Sung-Mo Kang
Pages: 291-296
doi>10.1145/277044.277129
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This paper presents a layout extraction and verification methodology which targets reliability-driven I/O design for CMOS VLSI chip, specifically to guard against electrostatic discharge (ESD) stress and latchup. We propose a new device extraction approach ...
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A mixed nodal-mesh formulation for efficient extraction and passive reduced-order modeling of 3D interconnects
Nuno Marques, Mattan Kamon, Jacob White, L. Miguel Silveira
Pages: 297-302
doi>10.1145/277044.277132
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As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate three-dimensional interconnect models. In this paper, we describe an integral equation aproach to modeling the impedance of inter-connect ...
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Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis
Byron Krauter, Sharad Mehrotra
Pages: 303-308
doi>10.1145/277044.277133
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It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines [7]. Furthermore, it is also understood that these circuits can be synthesized knowing only the ...
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A methodology for guided behavioral-level optimization
Lisa Guerra, Miodrag Potkonjak, Jan Rabaey
Pages: 309-314
doi>10.1145/277044.277134
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Optimization at the early stages of design are crucial. However, due to an overwhelming number of design and optimization options, design exploration is often conducted in a qualitative, ad-hoc manner. This paper presents a methodology and interactive ...
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A programming environment for the design of complex high speed ASICs
Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens
Pages: 315-320
doi>10.1145/277044.277135
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A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiv er is used as a driv er example. Compact descriptions, combined with efficient sim ulationand syn thesis strategies are ...
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Media architecture: general purpose vs. multiple application-specific programmable processor
Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith
Pages: 321-326
doi>10.1145/277044.277136
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In this paper we report a framework that makes it possible for a designer to rapidly explore the application-specific programmable processor design space under area constraints. The framework uses a production-quality compiler and simulation tools to ...
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User experience with high level formal verification (panel)
Randy E. Bryant, G. Musgrave
Page: 327
doi>10.1145/277044.277137
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Formal Verification is a “hot topic” for the user and vendor community. It has moved from the research community to the industrial domain in a very short time. Everyone wants to know more about how effective the techniques are. This experienced ...
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What's between simulation and formal verification? (extended abstract)
David L. Dill
Pages: 328-329
doi>10.1145/277044.277138
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This embedded tutorial surveys some possibilities for verification techniques that combine conventional simulation and ideas, techniques, and algorithms from formal verification, to obtain better functional test coverage of large designs.
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Optimal FPGA mapping and retiming with efficient initial state computation
Jason Cong, Chang Wu
Pages: 330-335
doi>10.1145/277044.277139
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For sequential circuits with given initial states, new equivalent initial states must be computed for retiming, which unfortunately is NP-hard. In this paper we propose a novel polynomial time algorithm for optimal FPGA mapping with forward ...
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M32: a constructive multilevel logic synthesis system
Victor N. Kravets, Karem A. Sakallah
Pages: 336-341
doi>10.1145/277044.277140
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We describe a new constructive multilevel logic synthesis system that integrates the traditionally separate technology-independent and technology-dependent stages of modern synthesis tools. Dubbed M32, this system is capable of generating circuits ...
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Efficient Boolean division and substitution
Shih-Chieh Chang, David Ihsin Cheng
Pages: 342-347
doi>10.1145/277044.277141
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Bo ole andivision, and henc eBo ole ansubstitution, produc es better result than algebraic division and substitution. However, due to the lack of an efficient Bo ole andivision algorithm, Bo ole ansubstitution has rarely b een used. We present ...
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Delay-optimal technology mapping by DAG covering
Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar
Pages: 348-351
doi>10.1145/277044.277142
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We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant ...
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A fast fanout optimization algorithm for near-continuous buffer libraries
David S. Kung
Pages: 352-355
doi>10.1145/277044.277143
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This paper presents a gain-based fanout optimization algorithm for near-continuous buffer libraries. A near-continuous buffer library contains many buffers in a wide range of discrete sizes and each buffer of a specific type satisfies a size-independent ...
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Performance driven multi-layer general area routing for PCB/MCM designs
Jason Cong, Patrick H. Madden
Pages: 356-361
doi>10.1145/277044.277144
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In this paper we present a new global router appropriate for Multichip Module (MCM) and dense Printed Circuit Board (PCB) design, which utilizes a hybrid of the classical rip-up and reroute approach, and the more recent iterative deletion [9] method. ...
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Buffer insertion for noise and delay optimization
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
Pages: 362-367
doi>10.1145/277044.277145
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Buffer insertion has successfully been applied to reduce delay in global interconnect paths; however, existing techniques only optimize delay and timing slack. With the increasing ratio of coupling to total capacitance and the use of aggressive ...
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Table-lookup methods for improved performance-driven routing
John Lillis, Premal Buch
Pages: 368-373
doi>10.1145/277044.277146
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The inaccuracy of Elmore delay [3] for inter conne ct delay estimation is well-documented. However it remains a popular delay measur e to drive p erformance optimization procedur es such as wire-sizing and topolo gy construction. This p aper ...
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Global routing with crosstalk constraints
Hai Zhou, D. F. Wong
Pages: 374-377
doi>10.1145/277044.277147
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Due to the scaling down of device geometry and increasing frequency in deep sub-micron designs, crosstalk between interconnection wires has become an important issue in VLSI layout design. In this paper, we consider crosstalk avoidance during global ...
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Timing and crosstalk driven area routing
Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
Pages: 378-381
doi>10.1145/277044.277148
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We present a timing and crosstalk driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a quantitative ...
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Process multi-circuit optimization
Arun Lokanathan, Jay Brockman
Pages: 382-387
doi>10.1145/277044.277149
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This paper describes the implementation of a concurrent methodology for integrated circuit optimization that spans the fabrication process design and circuit design disciplines. Results from this methodology show substantial performance gains as compared ...
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Migration: a new technique to improve synthesized designs through incremental customization
Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw
Pages: 388-391
doi>10.1145/277044.277150
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A novel technique to explore the performance vs design effort trade-off is proposed. Starting from an optimally synthesized design, performance-critical cells are incrementally and optimally selected and custom-sized to generate this ...
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A practical repeater insertion method in high speed VLSI circuits
Julian Culetu, Chaim Amir, John MacDonald
Pages: 392-395
doi>10.1145/277044.277151
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In today's design of VLSI high speed circuits, frequency has a major impact on the number of repeaters that needs to be inserted. A microprocessor operating at less than 200Mhz might require several hundred repeaters, while one operating at greater than ...
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Practical experiences with standard-cell based datapath design tools: do we really need regular layouts?
Paolo Ienne, Alexander Grießing
Pages: 396-401
doi>10.1145/277044.277152
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Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test circuits. Algorithmic generation of netlists and of relative cell ...
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A statistical performance simulation methodology for VLSI circuits
Michael Orshansky, James C. Chen, Chenming Hu
Pages: 402-407
doi>10.1145/277044.277153
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A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology ...
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RF IC design challenges
Behzad Razavi
Pages: 408-413
doi>10.1145/277044.277154
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This paper describes the challenges in designing RF integrated circuits for wireless transceiver applications. Receiver architectures such as heterodyne, homodyne, and image-reject topologies are presented and two transmitter architectures, namely, one-step ...
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Tools and methodology for RF IC design
Al Dunlop, Alper Demir, Peter Feldmann, Sharad Kapur, David Long, Robert Melville, Jaijeet Roychowdhury
Pages: 414-420
doi>10.1145/277044.277155
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We describe powerful new techniques for the analysis of RF circuits. Next-generation CAD tools based on such techniques should enable RF designers to obtain a more accurate picture of how their circuits will operate. These new simulation capabilities ...
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Electromagnetic modeling and signal integrity simulation of power/ground networks in high speed digital packages and printed circuit boards
Frank Y. Yuan
Pages: 421-426
doi>10.1145/277044.277164
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The electromagnetic modeling and parameter extraction of digital packages and PCB boards for system signal integrity applications are presented. A systematic approach to analyze complex power/ground structures and simulate their effects on digital systems ...
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Efficient coloring of a large spectrum of graphs
Darko Kirovski, Miodrag Potkonjak
Pages: 427-432
doi>10.1145/277044.277165
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We have developed a new algorithm and software for graph coloring by systematically combining several algorithm and software development ideas that had crucial impact on the algorithm's performance. The algorithm explores the divide-and-conquer ...
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Arithmetic optimization using carry-save-adders
Taewhan Kim, William Jao, Steve Tjiang
Pages: 433-438
doi>10.1145/277044.277166
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Carry-save-adder(CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer level design in industry. This paper establishes a relationship between the properties of arithmetic computations and ...
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Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions
Ganesh Lakshminarayana, Niraj K. Jha
Pages: 439-444
doi>10.1145/277044.277167
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We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex RTL modules, such as FFTs and filters, as building blocks for the RTL circuit, ...
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Approximation and decomposition of binary decision diagrams
Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi
Pages: 445-450
doi>10.1145/277044.277168
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Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and model checking algorithms have emphasized the need for efficient algorithms ...
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Approximate reachability with BDDs using overlapping projections
Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark A. Horowitz
Pages: 451-456
doi>10.1145/277044.277169
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Approximate reachability tec hniques trade off accuracy with the capacity to deal with bigger designs. Cho et al [3] proposed approximate FSM traversal algorithms over a partition of the set of state bits. In this paper w egeneralize ...
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Incremental CTL model checking using BDD subsetting
Abelardo Pardo, Gary D. Hachtel
Pages: 457-462
doi>10.1145/277044.277171
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An automatic abstraction/refinement algorithm for symbolic CTL model checking is presented. Conservative model checking is thus done for the full CTL language-no restriction is made to the universal or existen tial fragments. The algorithm begins with ...
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PRIMO: probability interpretation of moments for delay calculation
Rony Kay, Lawrence Pileggi
Pages: 463-468
doi>10.1145/277044.277172
Full text: PDFPDF

Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (first moment of the impulse response) expression, to moment matching methods which create reduced order transimpedance and transfer ...
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ftd: an exact frequency to time domain conversion for reduced order RLC interconnect models
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
Pages: 469-472
doi>10.1145/277044.277174
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Recursive convolution provides an exact solution for interfacing reduced-order frequency domain representations with discrete time domain models of piecewise linear voltage waveforms. The state-space method is more efficient, but not exact, and ...
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Extending moment computation to 2-port circuit representations
Fang-Jou Liu, Chung-Kuan Cheng
Pages: 473-476
doi>10.1145/277044.277176
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In this paper, we present an extension of moment computation to 2-port circuits. Our formulas are applicable to both transfer function moments and driving-point admittance moments. Given the input admittances, output admittances, and transfer functions ...
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Adjoint transient sensitivity computation in piecewise linear simulation
Tuyan V. Nguyen, Anirudh Devgan, Ognen J. Nastov
Pages: 477-482
doi>10.1145/277044.277177
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This paper presents a general method for computing transient sensitivities using the adjoint method in event driven simulation algorithms that employ piecewise linear device models. Sensitivity information provides first order assessment of circuit ...
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Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques
Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda
Pages: 483-488
doi>10.1145/277044.277178
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This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology ...
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Design and optimization of low voltage high performance dual threshold CMOS circuits
Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
Pages: 489-494
doi>10.1145/277044.277179
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Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in ...
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MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
James Kao, Siva Narendra, Anantha Chandrakasan
Pages: 495-500
doi>10.1145/277044.277180
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Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to provide adequate performance is difficult because the overall delay characteristics are strongly ...
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Technical challenges of IP and system-on-chip (panel): the ASIC vendor perspective
A. Richard Newton
Page: 501
doi>10.1145/277044.277181
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The vision of easily accessible IP that can be quickly integrated on silicon as “virtual components” is a compelling one, with deep implications for reuse methodology and EDA technology. Activities of the VSI Alliance, starting nearly two ...
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Software synthesis of process-based concurrent programs
Bill Lin
Pages: 502-505
doi>10.1145/277044.277182
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We present a Petri net theoretic approach to the software synthesis problem that can synthesize ordinary C programs from process-based concurrent specifications without the need for a run-time multi-threading environment. The synthesized C programs can ...
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Don't care-based BDD minimization for embedded software
Youpyo Hong, Peter A. Beerel, Luciano Lavagno, Ellen M. Sentovich
Pages: 506-509
doi>10.1145/277044.277183
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This paper explores the use of don't cares in software synthesis for embedded systems. Embedded systems have extremely tight real-time and code/data size constraints, that make expensive optimizations desirable. We propose applying BDD minimization ...
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Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
Silvina Hanono, Srinivas Devadas
Pages: 510-515
doi>10.1145/277044.277184
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The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures AVIV optimizes for minimum code size. Retargetable code generation requires the development of heuristic algorithms ...
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Code compression for embedded systems
Haris Lekatsas, Wayne Wolf
Pages: 516-521
doi>10.1145/277044.277185
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Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cache miss triggers the decompression of a main memory block, before ...
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A decision procedure for bit-vector arithmetic
Clark W. Barrett, David L. Dill, Jeremy R. Levitt
Pages: 522-527
doi>10.1145/277044.277186
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Bit-v ector theories with concatenation and extraction have been shown to be useful and important for hardware verification. We have implemented an extended theory which includes arithmetic. Although deciding equality in suc h a theory is NP-hard, our ...
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Functional vector generation for HDL models using linear programming and 3-satisfiability
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Pages: 528-533
doi>10.1145/277044.277187
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Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic and memory modules. Given a path in ...
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Automatic generation of assertions for formal verification of PowerPC microprocessor arrays using symbolic trajectory evaluation
Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy
Pages: 534-537
doi>10.1145/277044.277188
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For verifying complex sequen tialbloc ks such as microprocessor embedded arrays, the formal method of symbolic trajectory ev aluation (STE) has achieved great success in the past [[3], [5], [6]]. P ast STE methodology for arrays requires manual creation ...
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Combining theorem proving and trajectory evaluation in an industrial environment
Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger
Pages: 538-541
doi>10.1145/277044.277189
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We describe the verification of the IM: a large, complex (12,000gates and 1100 latches) circuit that detects and marks the boundariesbetween Intel architecture (IA-32) instructions. We verified agate-level model of the IM against an implementation-independentspecification ...
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A fast and low cost testing technique for core-based system-on-chip
Indradeep Ghosh, Sujit Dey, Niraj K. Jha
Pages: 542-547
doi>10.1145/277044.277190
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This paper proposes a new methodology for testing a core-based system-on-chip (SOC), targeting the simultaneous reduction of test area overhead and test application time. Testing of embedded cores is achieved using the transparency properties ...
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Introducing redundant computations in a behavior for reducing BIST resources
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Pages: 548-553
doi>10.1145/277044.277191
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The degree of freedom that can be exploited during scheduling and assignment to minimize BIST resources is often limited by the data dependencies of a behavior. W e propose transformation of a behavior by introducing redundant computations such that ...
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A BIST scheme for RTL controller-data paths based on symbolic testability analysis
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
Pages: 554-559
doi>10.1145/277044.277192
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This paper introduces a novel scheme for testing register-transfer level controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) which ...
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Figures of merit to characterize the importance of on-chip inductance
Yehea I. Ismail, Eby G. Friedman, Jose L. Neves
Pages: 560-565
doi>10.1145/277044.277193
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A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that ...
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Layout techniques for minimizing on-chip interconnect self inductance
Yehia Massoud, Steve Majors, Tareq Bustami, Jacob White
Pages: 566-571
doi>10.1145/277044.277194
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Because magnetic effects have a much longer spatial range than electrostatic effects, an interconnect line with large inductance will be sensitive to distant variations in interconnect topology. This long range sensitivity makes it difficult to balance ...
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A practical approach to static signal electromigration analysis
Nagaraj NS, Frank Cano, Haldun Haznedar, Duane Young
Pages: 572-577
doi>10.1145/277044.277195
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It is commonly thought that sweep-back effects would make electromigration (EM) a non-issue in signal lines. However this is only the case when the shape of the positive and negative current pulses are closely matched. Moreover, as performance pressures ...
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Design productivity (panel): how to measure it, how to improve it
Carlos Dangelo
Pages: 578-579
doi>10.1145/277044.277196
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“Design and Test” inputs and outputs can be viewed as generic interfaces between product creators (system designers) and IC manufacturing. The interface is actually a set of engineering processes which transform the design inputs (specifications ...
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Hierarchical functional timing analysis
Yuji Kukimoto, Robert K. Brayton
Pages: 580-585
doi>10.1145/277044.277197
Full text: PDFPDF

We propose a hierarchical timing analysis technique for combinational circuits under the tightest known sensitization criterion, the XBDO delay model. Given a hierarchical combinational circuit, a generalized delay model of each left module is characterized ...
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Making complex timing relationships readable: Presburger formula simplicication using don't cares
Tod Amon, Gaetano Borriello, Jiwen Liu
Pages: 586-590
doi>10.1145/277044.277198
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Solutions to timing relationship analysis problems are often reported using symbolic variables and inequalities which specify linear relationships between the variables. Complex relationships can be expressed using Presburger formulas which allow Boolean ...
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Delay estimation VLSI circuits from a high-level view
Mahadevamurty Nemani, Farid N. Najm
Pages: 591-594
doi>10.1145/277044.277199
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Estimation of the delay of a Boolean function from its functional description is an important step towards design exploration at the register transfer level (RTL). This paper addresses the problem of estimating the delay of certain optimal ...
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TETA: transistor-level engine for timing analysis
Florentin Dartu, Lawrence T. Pileggi
Pages: 595-598
doi>10.1145/277044.277200
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TETA is an interconnect-centric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and large coupled RC(L) interconnect models. TETA applies a novel compaction for the transistor ...
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Validation with guided search of the state space
C. Han Yang, David L. Dill
Pages: 599-604
doi>10.1145/277044.277201
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In practice, model checkers are most useful when they find bugs, not when they prove a property. However, because large portions of the state space of the design actually satisfy the specification, model checkers devote much effort verifying correct ...
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Efficient state classification of finite state Markov chains
Aiguo Xie, Peter A. Beerel
Pages: 605-610
doi>10.1145/277044.277202
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This paper presents an efficient method for state classification of finite state Markov chains using BDD-based symbolic techniques. The method exploits the fundamental properties of a Markov chain and classifies the state space by iteratively applying ...
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An implicit algorithm for finding steady states and its application to FSM verification
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
Pages: 611-614
doi>10.1145/277044.277203
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Finding the set of steady states of a machine has applications in formal verification, sequential synthesis and ATPG. Existing techniques assume the presence of a designated set of initial states which is impractical in a real design environment. ...
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Hybrid verification using saturated simulation
Adnan Aziz, Jim Kukula, Tom Shiple
Pages: 615-618
doi>10.1145/277044.277204
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We develop a verification paradigm called saturated simulation, that is applicable to designs which can be decomposed into a set of interacting controllers. The core procedure is a symbolic algorithm that explores the space of controller ...
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Fast state verification
Dechang Sun, Bapiraju Vinnakota, Wanli Jiang
Pages: 619-624
doi>10.1145/277044.277205
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Unique input/output(UIO) sequences are used for state verification and functional test in finite state machines. A UIO sequence for a state s distinguishes it from other states in the FSM. Current algorithms to compute UIO sequences are limited in their ...
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A fast sequential learning technique for real circuits with application to enhancing ATPG performance
Aiman El-Maleh, Mark Kassab, Janusz Rajski
Pages: 625-631
doi>10.1145/277044.277206
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This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve ...
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Fault-simulation based design error diagnosis for sequential circuits
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu
Pages: 632-637
doi>10.1145/277044.277207
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This paper addresses the problem of locating design errors in a sequential circuit. For single-error circuits, we consider a signal ƒ as a potential error source only if the circuit can be completely rectified by re-synthesizing ƒ (i.e., changing ...
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Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 microprocessor
Scott Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey
Pages: 638-643
doi>10.1145/277044.277208
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DIGITAL's Alpha 21264 processor is a highly out-of-order, superpipelined, superscalar implementation of the Alpha architecture, capable of a peak execution rate of six instructions per cycle and a sustainable rate of four per cycle. The 21264 also features ...
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Design reliability—estimation through statistical analysis of bug discovery data
Yossi Malka, Avi Ziv
Pages: 644-649
doi>10.1145/277044.277209
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Statistical analysis of bug discovery data is used in the software industry to check the quality of the testing process and estimate the reliability of the tested program. In this paper, we show that the same techniques are applicable to hardware design ...
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Functional verification of large ASICs
Adrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu
Pages: 650-655
doi>10.1145/277044.277210
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This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASICs designed at Nortel. These devices marked a transition point in methodology as verification took front and ...
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The EDA start-up experience (panel): the first product
Erach Desai
Pages: 656-657
doi>10.1145/277044.277211
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How does a novel EDA idea get transformed into a commercially successful product? Six veteran EDA entrepreneurs will discuss their experiences in bringing their companies' first products to market. Where did their ideas come from? How did they know their ...
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Digital system simulation: methodologies and examples
Kunle Olukotun, Mark Heinrich, David Ofelt
Pages: 658-663
doi>10.1145/277044.277212
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Two major trends in the digital design industry are the increase insystem complexity and the increasing importance of short designtimes. The rise in design complexity is motivated by consumerdemand for higher performance products as well as increases ...
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Hybrid techniques for fast functional simulation
Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz
Pages: 664-667
doi>10.1145/277044.277213
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W e implement and experiment with techniques for the functional simulation of very large digital systems. We consider techniques that are a hybrid of classical compiled code simulation and recent branching program based simulation in order to resolve ...
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A reconfigurable logic machine for fast event-driven simulation
Jerry Bauer, Michael Bershteyn, Ian Kaplan, Paul Vyedin
Pages: 668-671
doi>10.1145/277044.277214
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As the density of VLSI circuits increases, software techniques cannot effectively simulate designs through the millions of simulation cycles needed for verification. Emulation can supply the necessary capacity and performance, but emulation is limited ...
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Parallel algorithms for power estimation
Victor Kim, Prithviraj Banerjee
Pages: 672-677
doi>10.1145/277044.277215
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Sev eral tec hniques currently exist for estimating the pow er dissipation of combinational and sequen tialcircuits using exhaustive sim ulation,Monte Carlo sampling, and probabilistic estimation. Exhaustive sim ulation and Monte Carlo sampling techniques ...
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A power macromodeling technique based on power sensitivity
Zhanping Chen, Kaushik Roy
Pages: 678-683
doi>10.1145/277044.277216
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In this paper, we propose a novel power macromodeling technique for high level power estimation based on power sensitivity. Power sensitivity defines the change in average power due to changes in the input signal specification. The contribution of this ...
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Maximum power estimation using the limiting distributions of extreme order statistics
Qinru Qiu, Qing Wu, Massoud Pedram
Pages: 684-689
doi>10.1145/277044.277217
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In this paper we present a statistical method for estimating the maximum power consumption in VLSI circuits. The method is based on the theory of extreme order statistics applied to the probabilistic distribution of the cycle-based power consumption, ...
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An optimization-based error calculation for statistical power estimation of CMOS logic circuits
Byunggyu Kwak, Eun Sei Park
Pages: 690-693
doi>10.1145/277044.277218
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In this paper, we present a statistical power estimation method where estimation time and accuracy can be balanced by assigning smaller errors to the nodes with higher power dissipation and higher errors to the nodes with lower power dissipation. To ...
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Using complementation and resequencing to minimize transitions
Rajeev Murgai, Masahiro Fujita, Arlindo Oliveira
Pages: 694-697
doi>10.1145/277044.277219
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Recently, in [3], the following problem was addressed: Given a set of data words or messages to be transmitted over a bus such that the sequence (order) in which they are transmitted is irrelevant, determine the optimum sequence that minimizes ...
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Technology mapping for large complex PLDs
Jason Helge Anderson, Stephen Dean Brown
Pages: 698-703
doi>10.1145/277044.277220
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In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consists of a large number of PLA-style logic blocks. Although the traditional synthesis approach for such devices uses two-level minimization, the complexity ...
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Delay-optimal technology mapping for FPGAs with heterogeneous LUTs
Jason Cong, Songjie Xu
Pages: 704-707
doi>10.1145/277044.277221
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Recent generation of FPGAs take advantage of speed and density benefits resulted from heterogeneous FPGAs, which provide either an array of homogeneous programmable logic blocks (PLBs), each configured to implement circuits with lookup ...
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Exact tree-based FPGA technology mapping for logic blocks with independent LUTs
Madhukar R. Korupolu, K. K. Lee, D. F. Wong
Pages: 708-711
doi>10.1145/277044.277222
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The logic blocks (CLBs) of a lookup table (LUT) based FPGA consist of one or more LUTs, possibly of different sizes. In this paper, we focus on technology mapping for CLBs with several independent LUTs of two different sizes (called ...
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Compatible class encoding in hyper-function decomposition for FPGA synthesis
Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang
Pages: 712-717
doi>10.1145/277044.277223
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Recently, functional decomposition has been adopted for LUT based FPGA technology mapping with good results. In this paper, we propose a novel method for functional multiple-output decomposition. We first address a compatible class encoding method to ...
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In-place power optimization for LUT-based FPGAs
Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi
Pages: 718-721
doi>10.1145/277044.277224
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This paper presents a new technique to perform power-oriented re-configuration of a system implemented using LUT FPGAs. The main features of our approach are: Accurate exploitation of degrees of freedom, concurrent optimization of multiple LUTs ...
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A re-engineering approach to low power FPGA design using SPFD
Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang
Pages: 722-725
doi>10.1145/277044.277225
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In this paper, we present a method to re-synthesize Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) for low power design after technology mapping, placement and routing are performed. We use Set of Pairs of Functions to be Distinguished ...
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Power considerations in the design of the Alpha 21264 microprocessor
Michael K. Gowan, Larry L. Biro, Daniel B. Jackson
Pages: 726-731
doi>10.1145/277044.277226
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Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors ...
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Reducing power in high-performance microprocessors
Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez
Pages: 732-737
doi>10.1145/277044.277227
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Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. ...
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Design and analysis of power distribution networks in PowerPC microprocessors
Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
Pages: 738-743
doi>10.1145/277044.277229
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We present a methodology for the design and analysis of power grids in the PowerPC™ microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology ...
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Full-chip verification methods for DSM power distribution systems
Gregory Steele, David Overhauser, Steffen Rochel, Syed Zakir Hussain
Pages: 744-749
doi>10.1145/277044.277231
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Power distribution verification is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased load and reduced tolerances of DSM circuits, more failures are being seen due to poorly designed ...
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System chip test challenges, are there solutions today? (panel)
Prab Varma
Pages: 750-751
doi>10.1145/277044.277232
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To meet the challenges involved in designing systems on silicon, IC designers are increasingly adopting a design re-use methodology, in which pre-designed logic modules, often called virtual components (VC) or intellectual property (IP) cores, are integrated ...
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System-chip test strategies
Yervant Zorian
Pages: 752-757
doi>10.1145/277044.277234
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A major challenge in realizing core-based system-chips is theadoption of adequate test and diagnosis strategies. This paperfocuses on the current industrial practices in test strategiesfor system-chips. It discusses the challenges in testingembedded ...
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Finite state machine decomposition for low power
José C. Monteiro, Arlindo L. Oliveira
Pages: 758-763
doi>10.1145/277044.277235
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Clock-gating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. In this paper we describe a new clock-gating technique based on finite state machine (FSM) decomposition. We compute ...
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Computational kernels and their application to sequential power optimization
L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, M. Poncino
Pages: 764-769
doi>10.1145/277044.277237
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We introduce a new sequential optimization paradigm based on the extraction of computational kernels, i.e., logic blocks whose behavior mimics the steady-state behavior of the original circuit. We present a procedure for the automatic extraction ...
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Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions
Andrew Seawright, Wolfgang Meyer
Pages: 770-775
doi>10.1145/277044.277239
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This paper describes methods for partitioning and optimizing controllers described by hierarchical high-level descriptions. The methods utilize the structure of the high-level description, provide flexible exploration of the trade-off between ...
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Watermarking techniques for intellectual property protection
A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, G. Wolfe
Pages: 776-781
doi>10.1145/277044.277240
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Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and HDL program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based ...
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Robust IP watermarking methodologies for physical design
Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
Pages: 782-787
doi>10.1145/277044.277241
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Increasingly popular reuse-based design paradigms create a pressing need for authorship enforcement techniques that protect the intellectual property rights of designers. We develop the first intellectual property protection protocols for embedding design ...
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Data security for Web-based CAD
Scott Hauck, Stephen Knol
Pages: 788-793
doi>10.1145/277044.277242
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Internet-based computing has significant potential for improving most high-performance computing, including VLSI CAD. In this paper we consider the ramifications of the Internet on electronics design, and develop two models for Web-based CAD. We also ...
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Design of a SPDIF receiver using protocol compiler
Ulrich Holtmann, Peter Blinzer
Pages: 794-799
doi>10.1145/277044.277243
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This paper describes the design of a receiver for the digital audio signal SPDIF used by CD-ROM players. The design was done with Protocol Compiler, a high-level synthesis tool for the design of structured data stream processing controllers. Compared ...
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MetaCore: an application specific DSP development system
Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun-Sung Kim, Kwang-11 Park, Kyu-Ho Park, Yong-Hoon Lee, Seung-Hoon Hwang, In-Cheol Park, Chong-Min Kyung
Pages: 800-803
doi>10.1145/277044.277247
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This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications ...
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A case study in embedded system design: an engine control unit
Tullio Cuatto, Claudio Passeronge, Luciano Lavagno, Attila Jurecska, Antonino Damiano, Claudio Sansoè, A. Sangiovanni-Vincentelli, Alberto Sangiovanni-Vincentelli
Pages: 804-807
doi>10.1145/277044.277248
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A number of techniques and software tools for embedded system design have been recently proposed. However, the current practice in the designer community is heavily based on manual techniques and on past experience rather than on a rigorous approach ...
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HW/SW coverification performance estimation and benchmark for a 24 embedded RISC core design
Thomas W. Albrecht, Johann Notbauer, Stefan Rohringer
Pages: 808-811
doi>10.1145/277044.277250
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This paper describes the benchmarking of a HW/SW-coverification design strategy. The benchmark results were the base for making a principal verification decision for an already ongoing project at Siemens AG, Public Communication Network Group. The intention ...
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System-level exploration with SpecSyn
Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
Pages: 812-817
doi>10.1145/277044.277252
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We present the SpecSyn system-level design environment supp orting the sp ecify-explor e-refine (SER) designparadigm. This thr ee-step appr oach includes precise specification of system functionality, rapid explor ation of numerous system-level ...
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Author Index
Page: 818
Presentations from the 35th DAC: 35 years of design automation
Massoud Pedram
Page: 819

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