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Load execution latency reduction
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Authors:
Bryan Black
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Brian Mueller
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Stephanie Postal
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Ryan Rakvic
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Noppanunt Utamaphethai
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
John Paul Shen
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
1998 Article
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Published in:
· Proceeding
ICS '98 Proceedings of the 12th international conference on Supercomputing
Pages 29-36
ACM
New York, NY
, USA
©1998
table of contents
ISBN:0-89791-998-X
doi>
10.1145/277830.277842
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Tags:
design
experimentation
general
load address prediction
load execution
load/store alias
measurement
performance
reliability
speculative execution
theory
value prediction
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