An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors

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Authors: Catherine H. Gebotys Department of Electrical and Computer Engineering, University of Waterloo, Wilfrid Laurier University, Waterloo, Ont, Canada
Robert J. Gebotys
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· Proceeding
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Pages 121-123
ACM New York, NY, USA ©1998
table of contents ISBN:1-58113-059-7 doi>10.1145/280756.280824
An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors Published by ACM 1998 Article
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