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Architecture of a message-driven processor
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Authors:
William J. Dally
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Linda Chao
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Andrew Chien
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Soha Hassoun
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Waldemar Horwat
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Jon Kaplan
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Paul Song
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Brian Totty
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Scott Wills
Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
1998 Article
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Published in:
· Proceeding
ISCA '98
25 years of the international symposia on Computer architecture (selected papers)
Pages 337-344
ACM
New York, NY
, USA
©1998
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ISBN:1-58113-058-9
doi>
10.1145/285930.285993
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Tags:
design
instruction set design
measurement
multiple-instruction-stream, multiple-data-stream processors
performance
theory
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