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CITED BY123 Citations
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INDEX TERMSThe ACM Computing Classification System (CCS rev.2012)
PUBLICATION| · Proceeding | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Title | ASPLOS VIII Proceedings of the eighth international conference on Architectural support for programming languages and operating systems table of contents | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Chairmen | Dileep Bhandarkar Intel | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Anant Agarwal Massachusetts Institute of Technology, Cambridge | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Pages | 92-103 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Publication Date | 1998-10-01 (yyyy-mm-dd) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Sponsors | SIGARCH ACM Special Interest Group on Computer Architecture | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| SIGOPS ACM Special Interest Group on Operating Systems | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| SIGPLAN ACM Special Interest Group on Programming Languages | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| IEEE-CS Computer Society | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Publisher | ACM New York, NY, USA ©1998 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ISBN: 1-58113-107-0 Order Number: 556980 doi>10.1145/291069.291029 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Conference |
ASPLOSArchitectural Support for Programming Languages and Operating Systems
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| Paper Acceptance Rate 28 of 123 submissions, 23% | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Overall Acceptance Rate 503 of 2,475 submissions, 20% | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| · Newsletter | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Title | ACM SIGOPS Operating Systems Review Homepage table of contents archive | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Volume 32 Issue 5, Dec. 1998 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Editor | William M. Waite Univ. of Colorado, Boulder | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Pages | 92-103 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Publication Date | 1998-12-01 (yyyy-mm-dd) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Sponsor | SIGOPS ACM Special Interest Group on Operating Systems | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Publisher | ACM New York, NY, USA | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ISSN: 0163-5980 doi>10.1145/384265.291029 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| · Newsletter | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Title | ACM SIGPLAN Notices Homepage table of contents archive | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Volume 33 Issue 11, Nov. 1998 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Chairmen | Dileep Bhandarkar Intel | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Anant Agarwel Massachusetts Institute of Technology, Cambridge | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Pages | 92-103 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Publication Date | 1998-11-01 (yyyy-mm-dd) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Sponsor | SIGPLAN ACM Special Interest Group on Programming Languages | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Publisher | ACM New York, NY, USA | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ISSN: 0362-1340 EISSN: 1558-1160 doi>10.1145/291006.291029 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
REVIEWS
COMMENTSBe the first to comment To Post a comment please sign in or create a free Web account
Table of Contents| Compiler-controlled memory | |
| Keith D. Cooper, Timothy J. Harvey | |
| Pages: 2-11 | |
| doi>10.1145/291069.291010 | |
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Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a. reasonable level of success. The primary limit on the compiler's ability to improve memory ...
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| Segregating heap objects by reference behavior and lifetime | |
| Matthew L. Seidl, Benjamin G. Zorn | |
| Pages: 12-23 | |
| doi>10.1145/291069.291012 | |
Full text: PDF
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Dynamic storage allocation has become increasingly important in many applications, in part due to the use of the object-oriented paradigm. At the same time, processor speeds are increasing faster than memory speeds and programs are increasing in size ...
expand
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| Schedule-independent storage mapping for loops | |
| Michelle Mills Strout, Larry Carter, Jeanne Ferrante, Beth Simon | |
| Pages: 24-33 | |
| doi>10.1145/291069.291015 | |
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This paper studies the relationship between storage requirements and performance. Storage-related dependences inhibit optimizations for locality and parallelism. Techniques such as renaming and array expansion can eliminate all storage-related dependences, ...
expand
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| An empirical analysis of instruction repetition | |
| Avinash Sodani, Gurindar S. Sohi | |
| Pages: 35-45 | |
| doi>10.1145/291069.291016 | |
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We study the phenomenon of instruction repetition, where the inputs and outputs of multiple dynamic instances of a static instruction are repeated. We observe that over 80% of the dynamic instructions executed in several programs are repeated and most ...
expand
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| Space-time scheduling of instruction-level parallelism on a raw machine | |
| Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman Amarasinghe | |
| Pages: 46-57 | |
| doi>10.1145/291069.291018 | |
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Increasing demand for both greater parallelism and faster clocks dictate that future generation architectures will need to decentralize their resources and eliminate primitives that require single cycle global communication. A Raw microprocessor distributes ...
expand
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| Data speculation support for a chip multiprocessor | |
| Lance Hammond, Mark Willey, Kunle Olukotun | |
| Pages: 58-69 | |
| doi>10.1145/291069.291020 | |
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Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the support for threadlevel speculation on the Hydra chip multiprocessor (CMP). ...
expand
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| VISA: Netstation's virtual Internet SCSI adapter | |
| Rodney Van Meter, Gregory G. Finn, Steve Hotz | |
| Pages: 71-80 | |
| doi>10.1145/291069.291023 | |
Full text: PDF
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In this paper we describe the implementation of VISA, our Virtual Internet SCSI Adapter. VISA was built to evaluate the performance impact on the host operating system of using IP to communicate with peripherals, especially storage devices. We have built ...
expand
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| Active disks: programming model, algorithms and evaluation | |
| Anurag Acharya, Mustafa Uysal, Joel Saltz | |
| Pages: 81-91 | |
| doi>10.1145/291069.291026 | |
Full text: PDF
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Several application and technology trends indicate that it might be both profitable and feasible to move computation closer to the data that it processes. In this paper, we evaluate Active Disk architectures which integrate significant processing ...
expand
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| A cost-effective, high-bandwidth storage architecture | |
| Garth A. Gibson, David F. Nagle, Khalil Amiri, Jeff Butler, Fay W. Chang, Howard Gobioff, Charles Hardin, Erik Riedel, David Rochberg, Jim Zelenka | |
| Pages: 92-103 | |
| doi>10.1145/291069.291029 | |
Full text: PDF
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This paper describes the Network-Attached Secure Disk (NASD) storage architecture, prototype implementations oj NASD drives, array management for our architecture, and three, filesystems built on our prototype. NASD provides scalable storage bandwidth ...
expand
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| Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy | |
| Philip Machanick, Pierre Salverda, Lance Pompe | |
| Pages: 105-114 | |
| doi>10.1145/291069.291032 | |
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The RAMpage memory hierarchy is an alternative to the traditional division between cache and main memory: main memory is moved up a level and DRAM is used as a paging device. The idea behind RAMpage is to reduce hardware complexity, if at the cost of ...
expand
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| Dependence based prefetching for linked data structures | |
| Amir Roth, Andreas Moshovos, Gurindar S. Sohi | |
| Pages: 115-126 | |
| doi>10.1145/291069.291034 | |
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We introduce a dynamic scheme that captures the accesspat-terns of linked data structures and can be used to predict future accesses with high accuracy. Our technique exploits the dependence relationships that exist between loads that produce addresses ...
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| Performance counters and state sharing annotations: a unified approach to thread locality | |
| Boris Weissman | |
| Pages: 127-138 | |
| doi>10.1145/291069.291035 | |
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This paper describes a combined approach for improving thread locality that uses the bardware performance monitors of modem processors and program-centric code annotations to guide thread scheduling on SMPs. The approach relies on a shared state cache ...
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| Cache-conscious data placement | |
| Brad Calder, Chandra Krintz, Simmi John, Todd Austin | |
| Pages: 139-149 | |
| doi>10.1145/291069.291036 | |
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As the gap between memory and processor speeds continues to widen, cache eficiency is an increasingly important component of processor performance. Compiler techniques have been used to improve instruction cache pet$ormance by mapping code with temporal ...
expand
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| An out-of-order execution technique for runtime binary translators | |
| Bich C. Le | |
| Pages: 151-158 | |
| doi>10.1145/291069.291039 | |
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A dynamic translator emulates an instruction set architccturc by translating source instructions to native code during execution. On statically-scheduled hardware, higher performance can potentially be achieved by reordering the translated instructions; ...
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| Overlapping execution with transfer using non-strict execution for mobile programs | |
| Chandra Krintz, Brad Calder, Han Bok Lee, Benjamin G. Zorn | |
| Pages: 159-169 | |
| doi>10.1145/291069.291040 | |
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In order to execute a program on a remote computer, it mustfirst be transferred over a network. This transmission incurs the over-head of network latency before execution can begin. This latency can vary greatly depending upon the size of the program., ...
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| Variable length path branch prediction | |
| Jared Stark, Marius Evers, Yale N. Patt | |
| Pages: 170-179 | |
| doi>10.1145/291069.291042 | |
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Accurate branch prediction is required to achieve high performance in deeply pipelined, wide-issue processors. Recent studies have shown that conditional and indirect (or computed) branch targets can be accuratelypredicted by recording the path, which ...
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| Performance isolation: sharing and isolation in shared-memory multiprocessors | |
| Ben Verghese, Anoop Gupta, Mendel Rosenblum | |
| Pages: 181-192 | |
| doi>10.1145/291069.291044 | |
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Shared-memory multiprocessors (SMPs) are being extensively used as general-purpose servers. The tight coupling of multiple processors, memory, and I/O provides enormous computing power in a single system, and enables the efficient sharing of these resources.The ...
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| UTLB: a mechanism for address translation on network interfaces | |
| Yuqun Chen, Angelos Bilas, Stefanos N. Damianakis, Cezary Dubnicki, Kai Li | |
| Pages: 193-204 | |
| doi>10.1145/291069.291046 | |
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An important aspect of a high-speed network system is the ability to transfer data directly between the network interface and application buffers. Such a direct data path requires the network interface to "know" the virtual-to-physical address ...
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| Locality-aware request distribution in cluster-based network servers | |
| Vivek S. Pai, Mohit Aron, Gaurov Banga, Michael Svendsen, Peter Druschel, Willy Zwaenepoel, Erich Nahum | |
| Pages: 205-216 | |
| doi>10.1145/291069.291048 | |
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We consider cluster-based network servers in which a front-end directs incoming requests to one of a number of back-ends. Specifically, we consider content-based request distribution: the front-end uses the content requested, in addition to information ...
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| Investigating optimal local memory performance | |
| Olivier Temam | |
| Pages: 218-227 | |
| doi>10.1145/291069.291050 | |
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Recent work has demonstrated that, cache space is often poorly utilized. However, no previous work has yet demonstrated upper bounds on what a cache or local memory could achieve when exploiting both spatial and temporal locality. Belady's MIN algorithm ...
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| Precise miss analysis for program transformations with caches of arbitrary associativity | |
| Somnath Ghosh, Margaret Martonosi, Sharad Malik | |
| Pages: 228-239 | |
| doi>10.1145/291069.291051 | |
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Analyzing and optimizing program memory performance is a pressing problem in high-performance computer architectures. Currently, software solutions addressing the processor-memory performance gap include compiler-or programmer-applied optimizations like ...
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| Capturing dynamic memory reference behavior with adaptive cache topology | |
| Jih-Kwon Peir, Yongjoon Lee, Windsor W. Hsu | |
| Pages: 240-250 | |
| doi>10.1145/291069.291053 | |
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Memory references exhibit locality and are therefore not uniformly distributed across the sets of a cache. This skew reduces the effectiveness of a cache because it results in the caching of a considerable number of less-recently-used lines which are ...
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| Accelerating multi-media processing by implementing memoing in multiplication and division units | |
| Daniel Citron, Dror Feitelson, Larry Rudolph | |
| Pages: 252-261 | |
| doi>10.1145/291069.291056 | |
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This paper proposes a technique that enables performing multi-cycle (multiplication, division, square-root …) computations in a single cycle. The technique is based on the notion of memoing: saving the input and output of previous calculations ...
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| Value speculation scheduling for high performance processors | |
| Chao-Ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte | |
| Pages: 262-271 | |
| doi>10.1145/291069.291058 | |
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Recent research in value prediction shows a surprising amount of predictability for the values produced by register-writing instructions. Several hardware based value predictor designs have been proposed to exploit this predictability by eliminating ...
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| An empirical study of decentralized ILP execution models | |
| Narayan Ranganathan, Manoj Franklin | |
| Pages: 272-281 | |
| doi>10.1145/291069.291061 | |
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Recent fascination for dynamic scheduling as a means for exploiting instruction-level parallelism has introduced significant interest in the scalability aspects of dynamic scheduling hardware. In order to overcome the scalability problems of centralized ...
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| Fast out-of-order processor simulation using memoization | |
| Eric Schnarr, James R. Larus | |
| Pages: 283-294 | |
| doi>10.1145/291069.291063 | |
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Our new out-of-order processor simulatol; FastSim, uses two innovations to speed up simulation 8--15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy. First, FastSim uses speculative direct-execution to accelerate the functional ...
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| A look at several memory management units, TLB-refill mechanisms, and page table organizations | |
| Bruce L. Jacob, Trevor N. Mudge | |
| Pages: 295-306 | |
| doi>10.1145/291069.291065 | |
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Virtual memory is a staple in modem systems, though there is little agreement on how its functionality is to be implemented on either the hardware or software side of the interface. The myriad of design choices and incompatible hardware mechanisms suggests ...
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| Performance of database workloads on shared-memory systems with out-of-order processors | |
| Parthasarathy Ranganathan, Kourosh Gharachorloo, Sarita V. Adve, Luiz André Barroso | |
| Pages: 307-318 | |
| doi>10.1145/291069.291067 | |
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Database applications such as online transaction processing (OLTP) and decision support systems (DSS) constitute the largest and fastest-growing segment of the market for multiprocessor servers. However, most current system designs have been optimized ...
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