HSRA: high-speed, hierarchical synchronous reconfigurable array

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Authors: William Tsu Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Kip Macy Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Atul Joshi Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Randy Huang Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Norman Walker Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Tony Tung Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Omid Rowhani Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Varghese George Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
John Wawrzynek Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
André DeHon Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
HSRA: high-speed, hierarchical synchronous reconfigurable array Published by ACM 1999 Article
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· Proceeding
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Pages 125-134
ACM New York, NY, USA ©1999
table of contents ISBN:1-58113-088-0 doi>10.1145/296399.296442

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