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Efficient management of memory hierarchies in embedded DRAM systems
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Authors:
Ashley Saulsbury
Sun Microsystems Laboratories, 901 San Antonio Road, Palo Alto, CA
Su-Jaen Huang
Sun Microsystems Laboratories, 901 San Antonio Road, Palo Alto, CA
Fredrik Dahlgren
Dept. of Computer Engineering, Chalmers University of Technology, SE-413 05 Gothenburg, Sweden
Published in:
· Proceeding
ICS '99 Proceedings of the 13th international conference on Supercomputing
Pages 464-473
ACM
New York, NY
, USA
©1999
table of contents
ISBN:1-58113-164-X
doi>
10.1145/305138.305236
1999 Article
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Tags:
benchmarks
cache
coma
design
dram
dynamic memory
experimentation
latency
measurement
memory hierarchy
performance
processor
standardization
super computers
theory
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