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An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect |
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Jing-Rebecca Li,
Frank Wang,
Jacob K. White
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Pages: 1-6 |
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doi>10.1145/309847.309848 |
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Error bounded Padé approximation via bilinear conformal transformation |
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Chung-Ping Chen,
D. F. Wong
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Pages: 7-12 |
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doi>10.1145/309847.309850 |
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Model-reduction of nonlinear circuits using Krylov-space techniques |
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Pavan K. Gunupudi,
Michel S. Nakhla
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Pages: 13-16 |
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doi>10.1145/309847.309854 |
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ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization |
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Bernard N. Sheehan
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Pages: 17-21 |
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doi>10.1145/309847.309855 |
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Why is ATPG easy? |
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Mukul R. Prasad,
Philip Chong,
Kurt Keutzer
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Pages: 22-28 |
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doi>10.1145/309847.309857 |
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Using lower bounds during dynamic BDD minimization |
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Rolf Drechsler,
Wolfgang Günther
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Pages: 29-32 |
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doi>10.1145/309847.309858 |
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Optimization-intensive watermarking techniques for decision problems |
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Gang Qu,
Jennifer L. Wong,
Miodrag Potkonjak
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Pages: 33-36 |
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doi>10.1145/309847.309860 |
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Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems |
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Ali Dasdan,
Sandy S. Irani,
Rajesh K. Gupta
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Pages: 37-42 |
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doi>10.1145/309847.309862 |
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IP-based design methodology |
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Daniel D. Gajski
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Page: 43 |
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doi>10.1145/309847.309864 |
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ipChinook: an integrated IP-based design framework for distributed embedded systems |
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Pai Chou,
Ross Ortega,
Ken Hines,
Kurt Patridge,
Gaetano Borriello
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Pages: 44-49 |
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doi>10.1145/309847.309865 |
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Virtual simulation of distributed IP-based designs |
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Marcello Dalpasso,
Alessandro Bogliolo,
Luca Benini
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Pages: 50-55 |
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doi>10.1145/309847.309866 |
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Common-case computation: a high-level technique for power and performance optimization |
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Ganesh Lakshminarayana,
Anand Raghunathan,
Kamal S. Khouri,
Niraj K. Jha,
Sujit Dey
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Pages: 56-61 |
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doi>10.1145/309847.309867 |
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Layout techniques supporting the use of dual supply voltages for cell-based designs |
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Chingwei Yeh,
Yin-Shuin Kang,
Shan-Jih Shieh,
Jinn-Shyan Wang
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Pages: 62-67 |
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doi>10.1145/309847.309872 |
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Gate-level design exploiting dual supply voltages for power-driven applications |
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Chingwei Yeh,
Min-Cheng Chang,
Shih-Chieh Chang,
Wen-Bone Jone
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Pages: 68-71 |
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doi>10.1145/309847.309873 |
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Synthesis of low power CMOS VLSI circuits using dual supply voltages |
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Vijay Sundararajan,
Keshab K. Parhi
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Pages: 72-75 |
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doi>10.1145/309847.309876 |
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HW and SW in embedded system design: loveboat, shipwreck, or ships passing in the night |
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Raul Camposano,
Kurt Keutzer,
Jerry Fiddler,
Alberto Sangiovanni-Vincentelli,
Jim Lansford
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Pages: 76-77 |
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doi>10.1145/309847.309877 |
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Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings |
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Xiang-Dong Tan,
C.-J. Richard Shi,
Dragos Lungeanu,
Jyh-Chwen Lee,
Li-Pen Yuan
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Pages: 78-83 |
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doi>10.1145/309847.309880 |
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FAR-DS: full-plane AWE routing with driver sizing |
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Jiang Hu,
Sachin S. Sapatnekar
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Pages: 84-89 |
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doi>10.1145/309847.309881 |
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Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation |
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Hui-Ru Jiang,
Jing-Yang Jou,
Yao-Wen Chang
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Pages: 90-95 |
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doi>10.1145/309847.309882 |
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Simultaneous routing and buffer insertion with restrictions on buffer locations |
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Hai Zhou,
D. F. Wong,
I-Min Liu,
Adnan Aziz
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Pages: 96-99 |
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doi>10.1145/309847.309885 |
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Crosstalk minimization using wire perturbations |
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Prashant Saxena,
C. L. Liu
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Pages: 100-103 |
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doi>10.1145/309847.309887 |
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Practical advances in asynchronous design and in asynchronous/synchronous interfaces |
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Erik Brunvand,
Steven Nowick,
Kenneth Yun
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Pages: 104-109 |
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doi>10.1145/309847.309889 |
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Automatic synthesis and optimization of partially specified asynchronous systems |
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Alex Kondratyev,
Jordi Cortadella,
Michael Kishinevsky,
Luciano Lavagno,
Alexander Yakovlev
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Pages: 110-115 |
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doi>10.1145/309847.309891 |
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CAD directions for high performance asynchronous circuits |
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Ken Stevens,
Shai Rotem,
Steven M. Burns,
Jordi Cortadella,
Ran Ginosar,
Michael Kishinevsky,
Marly Roncken
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Pages: 116-121 |
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doi>10.1145/309847.309893 |
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A low power hardware/software partitioning approach for core-based embedded systems |
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Jörg Henkel
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Pages: 122-127 |
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doi>10.1145/309847.309896 |
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Synthesis of low-overhead interfaces for power-efficient communication over wide buses |
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L. Benini,
A. Macii,
E. Macii,
M. Poncino,
R. Scarsi
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Pages: 128-133 |
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doi>10.1145/309847.309898 |
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Power conscious fixed priority scheduling for hard real-time systems |
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Youngsoo Shin,
Kiyoung Choi
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Pages: 134-139 |
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doi>10.1145/309847.309901 |
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Memory exploration for low power, embedded systems |
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Wen-Tsong Shiue,
Chaitali Chakrabarti
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Pages: 140-145 |
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doi>10.1145/309847.309902 |
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Distributed application development with Inferno |
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Ravi Sharma
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Pages: 146-150 |
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doi>10.1145/309847.309904 |
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Embedded application design using a real-time OS |
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David Stepner,
Nagarajan Rajan,
David Hui
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Pages: 151-156 |
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doi>10.1145/309847.310566 |
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The Jini architecture: dynamic services in a flexible network |
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Ken Arnold
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Pages: 157-162 |
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doi>10.1145/309847.309906 |
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Verifying large-scale multiprocessors using an abstract verification environment |
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Dennis Abts,
Mike Roberts
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Pages: 163-168 |
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doi>10.1145/309847.309907 |
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Due to a patent dispute, full text of this article is not available
at this time.
Due to a patent dispute, full text of this article is not available
at this time.
expand
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Functional verification of the equator MAP1000 microprocessor |
| |
Jian Shen,
Jacob Abraham,
Dave Baker,
Tony Hurson,
Martin Kinkade,
Gregorio Gervasio,
Chen-chau Chu,
Guanghui Hu
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Pages: 169-174 |
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doi>10.1145/309847.309908 |
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Micro architecture coverage directed generation of test programs |
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Shmuel Ur,
Yaov Yadin
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Pages: 175-180 |
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doi>10.1145/309847.309909 |
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Verification of a microprocessor using real world applications |
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You-Sung Chang,
Seungjong Lee,
In-Cheol Park,
Chong-Min Kyung
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Pages: 181-184 |
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doi>10.1145/309847.311478 |
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High-level test generation for design verification of pipelined microprocessors |
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David Van Campenhout,
Trevor Mudge,
John P. Hayes
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Pages: 185-188 |
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doi>10.1145/309847.309912 |
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Developing an architecture validation suite: application to the PowerPC architecture |
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Laurent Fournier,
Anatoly Koyfman,
Moshe Levinger
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Pages: 189-194 |
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doi>10.1145/309847.309911 |
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Passive reduced-order models for interconnect simulation and their computation via Krylov-subspace algorithms |
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Roland W. Freund
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Pages: 195-200 |
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doi>10.1145/309847.309913 |
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Model order-reduction of RC(L) interconnect including variational analysis |
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Ying Liu,
Lawrence T. Pileggi,
Andrzej J. Strojwas
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Pages: 201-206 |
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doi>10.1145/309847.309914 |
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Robust rational function approximation algorithm for model generation |
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Carlos P. Coelho,
Joel R. Phillips,
L. Miguel Silveira
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Pages: 207-212 |
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doi>10.1145/309847.309915 |
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Behavioral network graph: unifying the domains of high-level and logic synthesis |
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Reinaldo A. Bergamaschi
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Pages: 213-218 |
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doi>10.1145/309847.309916 |
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Soft scheduling in high level synthesis |
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Jianwen Zhu,
Daniel D. Gajski
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Pages: 219-224 |
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doi>10.1145/309847.309917 |
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Graph coloring algorithms for fast evaluation of Curtis decompositions |
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Marek Perkowski,
Rahul Malvi,
Stan Grygiel,
Mike Burns,
Alan Mishchenko
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Pages: 225-230 |
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doi>10.1145/309847.309918 |
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Maximizing performance by retiming and clock skew scheduling |
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Xun Liu,
Marios C. Papaefthymiou,
Eby G. Friedman
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Pages: 231-236 |
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doi>10.1145/309847.309919 |
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A practical approach to multiple-class retiming |
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Klaus Eckl,
Jean Christophe Madre,
Peter Zepter,
Christian Legl
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Pages: 237-242 |
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doi>10.1145/309847.309920 |
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Performance-driven integration of retiming and resynthesis |
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Peichen Pan
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Pages: 243-246 |
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doi>10.1145/309847.309921 |
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Kernel-based power optimization of RTL components: exact and approximate extraction algorithms |
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L. Benini,
G. De Micheli,
E. Macii,
G. Odasso,
M. Poncino
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Pages: 247-252 |
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doi>10.1145/309847.309922 |
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Customized instruction-sets for embedded processors |
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Joseph A. Fisher
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Pages: 253-257 |
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doi>10.1145/309847.309923 |
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System-level hardware/software trade-offs |
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Samuel P. Harbison
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Pages: 258-259 |
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doi>10.1145/309847.309924 |
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Functional verification—real users, real problems, real opportunities (panel) |
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Nozar Azarakhsh,
Glen Ewing,
Paul Gingras,
Scott Reedstrom,
Chris Rowen /
Jonah McLeod
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Pages: 260-261 |
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doi>10.1145/309847.309925 |
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A timing-driven soft-macro resynthesis method in interaction with chip floorplanning |
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Hsiao-Pin Su,
Allen C.-H. Wu,
Youn-Long Lin
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Pages: 262-267 |
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doi>10.1145/309847.309926 |
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An O-tree representation of non-slicing floorplan and its applications |
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Pei-Ning Guo,
Chung-Kuan Cheng,
Takeshi Yoshimura
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Pages: 268-273 |
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doi>10.1145/309847.309928 |
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Module placement for analog layout using the sequence-pair representation |
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Florin Balasa,
Koen Lampaert
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Pages: 274-279 |
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doi>10.1145/309847.309930 |
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Genetic list scheduling algorithm for scheduling and allocation on a loosely coupled heterogeneous multiprocessor system |
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Martin Grajcar
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Pages: 280-285 |
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doi>10.1145/309847.309931 |
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Performance-driven scheduling with bit-level chaining |
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Sanghun Park,
Kiyoung Choi
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Pages: 286-291 |
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doi>10.1145/309847.309932 |
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A model for scheduling protocol-constrained components and environments |
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Steve Haynal,
Forrest Brewer
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Pages: 292-295 |
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doi>10.1145/309847.309933 |
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A reordering technique for efficient code motion |
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Luiz C. V. dos Santos,
Jochen A. G. Jess
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Pages: 296-299 |
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doi>10.1145/309847.309935 |
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Coverage estimation for symbolic model checking |
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Yatin Hoskote,
Timothy Kam,
Pei-Hsin Ho,
Xudong Zhao
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Pages: 300-305 |
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doi>10.1145/309847.309936 |
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Improving symbolic traversals by means of activity profiles |
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Gianpiero Cabodi,
Paolo Camurati,
Stefano Quer
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Pages: 306-311 |
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doi>10.1145/309847.309938 |
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Improved approximate reachability using auxiliary state variables |
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Shankar G. Govindaraju,
David L. Dill,
Jules P. Bergmann
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Pages: 312-316 |
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doi>10.1145/309847.309940 |
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Symbolic model checking using SAT procedures instead of BDDs |
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A. Biere,
A. Cimatti,
E. M. Clarke,
M. Fujita,
Y. Zhu
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Pages: 317-320 |
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doi>10.1145/309847.309942 |
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Power efficient mediaprocessors: design space exploration |
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Johnson Kin,
Chunho Lee,
William H. Mangione-Smith,
Miodrag Potkonjak
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Pages: 321-326 |
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doi>10.1145/309847.309943 |
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Global multimedia system design exploration using accurate memory organization feedback |
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Arnout Vandecappelle,
Miguel Miranda,
Erik Brockmeyer,
Francky Catthoor,
Diederik Verkest
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Pages: 327-332 |
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doi>10.1145/309847.309945 |
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Implementation of a scalable MPEG-4 wavelet-based visual texture compression system |
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L. Nachtergaele,
B. Vanhoof,
M. Peón,
G. Lafruit,
J. Bormans,
I. Bolsens
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Pages: 333-336 |
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doi>10.1145/309847.309948 |
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A 10 Mbit/s upstream cable modem with automatic equalization |
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Patrick Schaumont,
Radim Cmar,
Serge Vernalde,
Marc Engels
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Pages: 337-340 |
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doi>10.1145/309847.309950 |
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Cell libraries—build vs. buy; static vs. dynamic (panel) |
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Kurt Wolf,
David Pietromonaco,
Jay Maxey,
Jeff Lewis,
Martin Lefebvre,
Jeff Burns /
Kurt Keutzer
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Pages: 341-342 |
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doi>10.1145/309847.309951 |
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Multilevel k-way hypergraph partitioning |
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George Karypis,
Vipin Kumar
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Pages: 343-348 |
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doi>10.1145/309847.309954 |
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Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting |
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Andrew E. Caldwell,
Andrew B. Kahng,
Andrew A. Kennings,
Igor L. Markov
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Pages: 349-354 |
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doi>10.1145/309847.309955 |
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Hypergraph partitioning with fixed vertices |
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Andrew E. Caldwell,
Andrew B. Kahng,
Igor L. Markov
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Pages: 355-359 |
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doi>10.1145/309847.309957 |
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Relaxation and clustering in a local search framework: application to linear placement |
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Sung-Woo Hur,
John Lillis
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Pages: 360-366 |
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doi>10.1145/309847.309958 |
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An &agr;-approxmimate algorithm for delay-constraint technology mapping |
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Sumit Roy,
Krishna Belkhale,
Prithviraj Banerjee
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Pages: 367-372 |
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doi>10.1145/309847.309960 |
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Technology mapping for FPGAs with nonuniform pin delays and fast interconnections |
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Jason Cong,
Yean-Yow Hwang,
Songjie Xu
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Pages: 373-378 |
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doi>10.1145/309847.309963 |
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Automated phase assignment for the synthesis of low power domino circuits |
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Priyadarshan Patra,
Unni Narayanan
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Pages: 379-384 |
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doi>10.1145/309847.309964 |
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Enhancing simulation with BDDs and ATPG |
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Malay K. Ganai,
Adnan Aziz,
Andreas Kuehlmann
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Pages: 385-390 |
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doi>10.1145/309847.309965 |
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Cycle-based symbolic simulation of gate-level synchronous circuits |
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Valeria Bertacco,
Maurizio Damiani,
Stefano Quer
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Pages: 391-396 |
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doi>10.1145/309847.309966 |
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Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors |
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Miroslav N. Velev,
Randal E. Bryant
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Pages: 397-401 |
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doi>10.1145/309847.309967 |
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Formal verification using parametric representations of Boolean constraints |
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Mark D. Aagaard,
Robert B. Jones,
Carl-Johan H. Serger
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Pages: 402-407 |
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doi>10.1145/309847.309968 |
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Vertical benchmarks for CAD |
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Christopher Inacio,
Herman Schmit,
David Nagle,
Andrew Ryan,
Donald E. Thomas,
Yingfai Tong,
Ben Klass
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Pages: 408-413 |
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doi>10.1145/309847.309969 |
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A framework for user assisted design space exploration |
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X. Hu,
G. W Greenwood,
S. Ravichandran,
G. Quan
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Pages: 414-419 |
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doi>10.1145/309847.309970 |
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Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design |
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Benoit Clement,
Richard Hersemeule,
Etienne Lantreibecq,
Bernard Ramanadin,
Pierre Coulomb,
Francois Pogodalla
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Pages: 420-424 |
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doi>10.1145/309847.309971 |
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Verification and management of a multimillion-gate embedded core design |
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Johann Notbauer,
Thomas Albrecht,
Georg Niedrist,
Stefan Rohringer
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Pages: 425-428 |
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doi>10.1145/309847.309972 |
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Parasitic extraction accuracy; how much is enough? (panel) |
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Mark Basel,
Aki Fujimara,
Sharad Mehrotra,
Ron Preston,
Robin C. Sarma,
Marty Walker /
Paul Franzon
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Page: 429 |
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doi>10.1145/309847.309973 |
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Mixed-Vth (MVT) CMOS circuit design methodology for low power applications |
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Liqiong Wei,
Zhanping Chen,
Kaushik Roy,
Yibin Ye,
Vivek De
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Pages: 430-435 |
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doi>10.1145/309847.309974 |
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Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing |
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Supamas Sirichotiyakul,
Tim Edwards,
Chanhee Oh,
Jingyan Zuo,
Abhijit Dharchoudhury,
Rajendran Panda,
David Blaauw
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Pages: 436-441 |
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doi>10.1145/309847.309975 |
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Leakage control with efficient use of transistor stacks in single threshold CMOS |
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Mark C. Johnson,
Dinesh Somasekhar,
Kaushik Roy
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Pages: 442-445 |
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doi>10.1145/309847.309976 |
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A practical gate resizing technique considering glitch reduction for low power design |
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Masanori Hashimoto,
Hidetoshi Onodera,
Keikichi Tamaru
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Pages: 446-451 |
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doi>10.1145/309847.309977 |
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Gradient-based optimization of custom circuits using a static-timing formulation |
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A. R. Conn,
I. M. Elfadel,
W. W. Molzen, Jr.,
P. R. O'Brien,
P. N. Strenski,
C. Visweswariah,
C. B. Whan
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Pages: 452-459 |
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doi>10.1145/309847.309979 |
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Simultaneous circuit partitioning/clustering with retiming for performance optimization |
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Jason Cong,
Honching Li,
Chang Wu
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Pages: 460-465 |
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doi>10.1145/309847.309980 |
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Wave steering in YADDs: a novel non-iterative synthesis and layout technique |
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Arindam Mukherjee,
Ranganathan Sudhakar,
Malgorzata Marek-Sadowska,
Stephen I. Long
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Pages: 466-471 |
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doi>10.1145/309847.309981 |
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MERLIN: semi-order-independent hierarchical buffered routing tree generation using local neighborhood search |
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Amir H. Salek,
Jinan Lou,
Massoud Pedram
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Pages: 472-478 |
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doi>10.1145/309847.309982 |
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Buffer insertion with accurate gate and interconnect delay computation |
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Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay
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Pages: 479-484 |
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doi>10.1145/309847.309983 |
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Reducing cross-coupling among interconnect wires in deep-submicron datapath design |
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Joon-Seo Yim,
Chong-Min Kyung
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Pages: 485-490 |
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doi>10.1145/309847.309984 |
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A novel VLSI layout fabric for deep sub-micron applications |
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Sunil P. Khatri,
Amit Mehrotra,
Robert K. Brayton,
Ralf H. J. M. Otten,
Alberto Sangiovanni-Vincentelli
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Pages: 491-496 |
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doi>10.1145/309847.309985 |
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Improved delay prediction for on-chip buses |
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Real G. Pomerleau,
Paul D. Frazon,
Griff L. Bilbro
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Pages: 497-501 |
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doi>10.1145/309847.309986 |
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Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching |
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Chung-Ping Chen,
Noel Menezes
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Pages: 502-506 |
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doi>10.1145/309847.309987 |
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Interconnect estimation and planning for deep submicron designs |
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Jason Cong,
David Zhigang Pan
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Pages: 507-510 |
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doi>10.1145/309847.309988 |
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ECL: a specification environment for system-level design |
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Luciano Lavagno,
Ellen Sentovich
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Pages: 511-516 |
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doi>10.1145/309847.309989 |
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Representation of function variants for embedded system optimization and synthesis |
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K. Richter,
D. Ziegenbein,
R. Ernst,
L. Thiele,
J. Teich
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Pages: 517-522 |
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doi>10.1145/309847.309990 |
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Vex—A CAD toolbox |
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Jules P. Bergmann,
Mark A. Horowitz
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Pages: 523-528 |
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doi>10.1145/309847.309991 |
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Constraint management for collaborative electronic design |
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Juan Antonio Carballo,
Stephen W. Director
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Pages: 529-534 |
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doi>10.1145/309847.309992 |
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MEMS CAD beyond multi-million transistors (panel) |
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Albert P. Pisano,
Nicholas Swart,
Mike Horton,
John Rychcik,
John R. Gilbert,
Gerry K. Fedder /
Kris Pister
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Pages: 535-536 |
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doi>10.1145/309847.309993 |
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A multiscale method for fast capacitance extraction |
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Johannes Tausch,
Jacob White
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Pages: 537-542 |
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doi>10.1145/309847.309994 |
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Efficient capacitance computation for structures with non-uniform adaptive surface meshes |
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Vikram Jandhyala,
Scott Savage,
Eric Bracken,
Zoltan Cendes
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Pages: 543-548 |
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doi>10.1145/309847.309995 |
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Substrate modeling and lumped substrate resistance extraction for CMOS ESD/latchup circuit simulation |
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Tong Li,
Ching-Han Tsai,
Elyse Rosenbaum,
Sung-Mo Kang
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Pages: 549-554 |
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doi>10.1145/309847.309996 |
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Dynamic power management based on continuous-time Markov decision processes |
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Qinru Qiu,
Massoud Pedram
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Pages: 555-561 |
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doi>10.1145/309847.309997 |
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Parallel mixed-level power simulation based on spatio-temporal circuit partitioning |
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Mauro Chinosi,
Roberto Zafalon,
Carlo Guardiani
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Pages: 562-567 |
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doi>10.1145/309847.309998 |
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Low-power behavioral synthesis optimization using multiple precision arithmetic |
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Milos Ercegovac,
Darko Kirovski,
Miodrag Potkonjak
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Pages: 568-573 |
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doi>10.1145/309847.310000 |
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A methodology for the verification of a “system on chip” |
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Daniel Geist,
Giora Biran,
Tamara Arons,
Michael Slavkin,
Yvgeny Nustov,
Monica Farkas,
Karen Holtz,
Andy Long,
Dave King,
Steve Barret
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Pages: 574-579 |
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doi>10.1145/309847.310001 |
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ICEBERG: an embedded in-circuit emulator synthesizer for microcontrollers |
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Ing-Jer Huang,
Tai-An Lu
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Pages: 580-585 |
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doi>10.1145/309847.310003 |
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Microprocessor based testing for core-based system on chip |
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C. A. Papachristou,
F. Martin,
M. Nourani
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Pages: 586-591 |
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doi>10.1145/309847.310004 |
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Using partitioning to help convergence in the standard-cell design automation methodology |
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Hema Kapadia,
Mark Horowitz
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Pages: 592-597 |
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doi>10.1145/309847.310005 |
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Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper |
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Imed Moussa,
Zoltan Sugar,
Rodolph Suescun,
Mario Diaz-Nava,
Marco Pavesi,
Salvatore Crudo,
Luca Gazi,
Ahmed Amine Jerraya
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Pages: 598-603 |
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doi>10.1145/309847.310006 |
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Engineering change: methodology and applications to behavioral and system synthesis |
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Darko Kirovski,
Miodrag Potkonjak
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Pages: 604-609 |
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doi>10.1145/309847.310007 |
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Reconfigurable computing: what, why, and implications for design automation |
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André DeHon,
John Wawrzynek
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Pages: 610-615 |
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doi>10.1145/309847.310009 |
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An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications |
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Meenakshi Kaul,
Ranga Vemuri,
Sriram Govindarajan,
Iyad Ouaiss
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Pages: 616-622 |
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doi>10.1145/309847.310010 |
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Dynamically reconfigurable architecture for image processor applications |
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Alexandro M. S. Adário,
Eduardo L. Roehe,
Sergio Bampi
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Pages: 623-628 |
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doi>10.1145/309847.310012 |
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Multi-time simulation of voltage-controlled oscillators |
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Onuttom Narayan,
Jaijeet Roychowdhury
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Pages: 629-634 |
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doi>10.1145/309847.310014 |
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Efficient computation of quasi-periodic circuit operating conditions via a mixed frequency/time approach |
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Dan Feng,
Joel Phillips,
Keith Nabors,
Ken Kundert,
Jacob White
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Pages: 635-640 |
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doi>10.1145/309847.310015 |
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Time-mapped harmonic balance |
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Ognen J. Nastov,
Jacob K. White
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Pages: 641-646 |
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doi>10.1145/309847.310016 |
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Test generation for Gigahertz processors using an automatic functional constraint extractor |
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Raghuram S. Tupuri,
Arun Krishnamachary,
Jacob A. Abraham
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Pages: 647-652 |
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doi>10.1145/309847.310018 |
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Proptest: a property based test pattern generator for sequential circuits using test compaction |
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Ruifeng Guo,
Sudhakar M. Reddy,
Irith Pomeranz
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Pages: 653-659 |
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doi>10.1145/309847.310019 |
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Multiple error diagnosis based on xlists |
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Vamsi Boppana,
Rajarshi Mukherjee,
Jawahar Jain,
Masahiro Fujita,
Pradeep Bollineni
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Pages: 660-665 |
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doi>10.1145/309847.310021 |
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Simulation vector generation from HDL descriptions for observability-enhanced statement coverage |
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Farzan Fallah,
Pranav Ashar,
Srinivas Devadas
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Pages: 666-671 |
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doi>10.1145/309847.310023 |
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A two-state methodology for RTL logic simulation |
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Lionel Bening
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Pages: 672-677 |
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doi>10.1145/309847.310024 |
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An approach for extracting RT timing information to annotate algorithmic VHDL specifications |
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Cordula Hansen,
Francisco Nascimento,
Wolfgang Rosenstiel
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Pages: 678-683 |
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doi>10.1145/309847.310026 |
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A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware |
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Miron Abramovici,
Jose T. de Sousa,
Daniel Saab
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Pages: 684-690 |
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doi>10.1145/309847.310028 |
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Dynamic fault diagnosis on reconfigurable hardware |
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Fatih Kocan,
Daniel G. Saab
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Pages: 691-696 |
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doi>10.1145/309847.310029 |
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Hardware compilation for FPGA-based configurable computing machines |
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Xiaohan Zhu,
Bill Lin
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Pages: 697-702 |
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doi>10.1145/309847.310030 |
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0.18μm CMOS and beyond |
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D. J. Eaglesham
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Pages: 703-708 |
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doi>10.1145/309847.310032 |
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SOI digital CMOS VLSI—a design perspective |
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C. T. Chuang,
R. Puri
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Pages: 709-714 |
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doi>10.1145/309847.310034 |
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Equivalent Elmore delay for RLC trees |
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Yehea I. Ismail,
Eby G. Friedman,
Jose L. Neves
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Pages: 715-720 |
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doi>10.1145/309847.310041 |
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Effects of inductance on the propagation delay and repeater insertion in VLSI circuits |
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Yehea I. Ismail,
Eby G. Friedman
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Pages: 721-724 |
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doi>10.1145/309847.310042 |
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Retiming for DSM with area-delay trade-offs and delay constraints |
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Abdallah Tabbara,
Robert K. Brayton,
A. Richard Newton
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Pages: 725-730 |
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doi>10.1145/309847.310044 |
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Functional timing analysis for IP characterization |
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Hakan Yalcin,
Mohammad Mortazavi,
Robert Palermo,
Cyrus Bamji,
Karem Sakallah
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Pages: 731-736 |
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doi>10.1145/309847.310045 |
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Detecting false timing paths: experiments on PowerPC microprocessors |
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Richard Raimi,
Jacob Abraham
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Pages: 737-741 |
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doi>10.1145/309847.310047 |
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On ILP formulations for built-in self-testable data path synthesis |
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Han Bin Kim,
Dong Sam Ha,
Takeshi Takahashi
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Pages: 742-747 |
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doi>10.1145/309847.310048 |
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Improving the test quality for scan-based BIST using a general test application scheme |
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Huan-Chih Tsai,
Kwang-Tin Cheng,
Sudipta Bhawmik
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Pages: 748-753 |
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doi>10.1145/309847.310050 |
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Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences |
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Irith Pomeranz,
Sudhakar M. Reddy
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Pages: 754-759 |
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doi>10.1145/309847.310052 |
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Analysis of performance impact caused by power supply noise in deep submicron devices |
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Yi-Min Jiang,
Kwang-Ting Cheng
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Pages: 760-765 |
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doi>10.1145/309847.310053 |
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A floorplan-based planning methodology for power and clock distribution in ASICs |
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Joon-Seo Yim,
Seong-Ok Bae,
Chong-Min Kyung
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Pages: 766-771 |
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doi>10.1145/309847.310054 |
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Digital detection of analog parametric faults in SC filters |
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Ramesh Harjani,
Bapiraju Vinnakota
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Pages: 772-777 |
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doi>10.1145/309847.310056 |
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Application of high level interface-based design to telecommunications system hardware |
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Dyson Wilkes,
M. M. Kamal Hashmi
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Pages: 778-783 |
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doi>10.1145/309847.310057 |
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Hardware reuse at the behavioral level |
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Patrick Schaumont,
Radim Cmar,
Serge Vernalde,
Marc Engels,
Ivo Bolsens
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Pages: 784-789 |
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doi>10.1145/309847.310058 |
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Description and simulation of hardware/software systems with Java |
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Tommy Kuhn,
Wolfgang Rosenstiel,
Udo Kebschull
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Pages: 790-793 |
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doi>10.1145/309847.310059 |
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Java driven codesign and prototyping of networked embedded systems |
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Josef Fleischmann,
Klaus Buchenrieder,
Rainer Kress
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Pages: 794-797 |
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doi>10.1145/309847.310068 |
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Subwavelength lithography (panel): how will it affect your design flow? |
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Y. C. Pati,
Warren Grobman,
Robert Pack,
Lance Glasser /
Andrew B. Kahng
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Page: 798 |
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doi>10.1145/309847.310070 |
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Subwavelength lithography and its potential impact on design and EDA |
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Andrew B. Kahng,
Y. C. Pati
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Pages: 799-804 |
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doi>10.1145/309847.310072 |
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Synthesis of embedded software using free-choice Petri nets |
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Marco Sgroi,
Luciano Lavagno,
Yosinori Watanabe,
Alberto Sangiovanni-Vincentelli
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Pages: 805-810 |
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doi>10.1145/309847.310073 |
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Exact memory size estimation for array computations without loop unrolling |
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Ying Zhao,
Sharad Malik
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Pages: 811-816 |
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doi>10.1145/309847.310074 |
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Constraint driven code selection for fixed-point DSPs |
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Steven Bashford,
Rainer Leupers
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Pages: 817-822 |
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doi>10.1145/309847.310076 |
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Rapid development of optimized DSP code from a high level description through software estimations |
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Alain Pegatoquet,
Emmanuel Gresset,
Michel Auguin,
Luc Bianco
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Pages: 823-826 |
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doi>10.1145/309847.310077 |
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Software environment for a multiprocessor DSP |
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Asawaree Kalavade,
Joe Othmer,
Bryan Ackland,
K. J. Singh
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Pages: 827-830 |
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doi>10.1145/309847.310078 |
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Robust FPGA intellectual property protection through multiple small watermarks |
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John Lach,
William H. Mangione-Smith,
Miodrag Potkonjak
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Pages: 831-836 |
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doi>10.1145/309847.310080 |
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Robust techniques for watermarking sequential circuit designs |
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Arlindo L. Oliveira
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Pages: 837-842 |
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doi>10.1145/309847.310082 |
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Effective iterative techniques for fingerprinting design IP |
| |
Andrew E. Caldwell,
Hyun-Jin Choi,
Andrew B. Kahng,
Stefanus Mantik,
Miodrag Potkonjak,
Gang Qu,
Jennifer L. Wong
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Pages: 843-848 |
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doi>10.1145/309847.310083 |
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Behavioral synthesis techniques for intellectual property protection |
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Inki Hong,
Miodrag Potkonjak
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Pages: 849-854 |
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doi>10.1145/309847.310085 |
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Design and implementation of a scalable encryption processor with embedded variable DC/DC converter |
| |
James Goodman,
Anantha Chandrakasan,
Abram P. Dancy
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Pages: 855-860 |
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doi>10.1145/309847.310087 |
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Design considerations for battery-powered electronics |
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Massoud Pedram,
Qing Wu
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Pages: 861-866 |
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doi>10.1145/309847.310089 |
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Cycle-accurate simulation of energy consumption in embedded systems |
| |
Tajana Šimunić,
Luca Benini,
Giovanni De Micheli
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Pages: 867-872 |
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doi>10.1145/309847.310090 |
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Lowering power consumption in clock by using globally asynchronous locally synchronous design style |
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A. Hemani,
T. Meincke,
S. Kumar,
A. Postula,
T. Olsson,
P. Nilsson,
J. Oberg,
P. Ellervee,
D. Lundqvist
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Pages: 873-878 |
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doi>10.1145/309847.310091 |
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A CAD tool for optical MEMS |
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Timothy P. Kurzweg,
Steven P. Levitan,
Philippe J. Marchand,
Jose A. Martinez,
Kurt R. Prough,
Donald M. Chiarulli
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Pages: 879-884 |
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doi>10.1145/309847.310092 |
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On thermal effects in deep sub-micron VLSI interconnects |
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Kaustav Banerjee,
Amit Mehrotra,
Alberto Sangiovanni-Vincentelli,
Chenming Hu
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Pages: 885-891 |
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doi>10.1145/309847.310093 |
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Converting a 64b PowerPC processor from CMOS bulk to SOI technology |
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D. Allen,
D. Behrends,
B. Stanisic
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Pages: 892-897 |
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doi>10.1145/309847.310094 |
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A framework for collaborative and distributed web-based design |
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Gangadhar Konduri,
Anantha Chandrakasan
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Pages: 898-903 |
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doi>10.1145/309847.310095 |
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Dealing with inductance in high-speed chip design |
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Phillip Restle,
Albert Ruehli,
Steven G. Walker
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Pages: 904-909 |
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doi>10.1145/309847.310096 |
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Interconnect analysis: from 3-D structures to circuit models |
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M. Kamon,
N. Marques,
Y. Massoud,
L. Silveira,
J. White
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Pages: 910-914 |
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doi>10.1145/309847.310097 |
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IC analyses including extracted inductance models |
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Michael W. Beattie,
Lawrence T. Pileggi
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Pages: 915-920 |
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doi>10.1145/309847.310098 |
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On-chip inductance issues in multiconductor systems |
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Shannon V. Morton
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Pages: 921-926 |
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doi>10.1145/309847.310099 |
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A methodology for accurate performance evaluation in architecture exploration |
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George Hadjiyiannis,
Pietro Russo,
Srinivas Devadas
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Pages: 927-932 |
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doi>10.1145/309847.310100 |
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LISA—machine description language for cycle-accurate models of programmable DSP architectures |
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Stefan Pees,
Andreas Hoffmann,
Vojin Zivojnovic,
Heinrich Meyr
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Pages: 933-938 |
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doi>10.1145/309847.310101 |
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Exploiting intellectual properties in ASIP designs for embedded DSP software |
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Hoon Choi,
Ju Hwan Yi,
Jong-Yeol Lee,
In-Cheol Park,
Chong-Min Kyung
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Pages: 939-944 |
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doi>10.1145/309847.310103 |
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MAELSTROM: efficient simulation-based synthesis for custom analog cells |
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Michael Krasnicki,
Rodney Phelps,
Rob A. Rutenbar,
L. Richard Carley
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Pages: 945-950 |
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doi>10.1145/309847.310104 |
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Behavioral synthesis of analog systems using two-layered design space exploration |
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Alex Doboli,
Adrian Nunez-Aldana,
Nagu Dhanwada,
Sree Ganesan,
Ranga Vemuri
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Pages: 951-957 |
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doi>10.1145/309847.310105 |
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Circuit complexity reduction for symbolic analysis of analog integrated circuits |
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Walter Daems,
Georges Gielen,
Willy Sansen
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Pages: 958-963 |
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doi>10.1145/309847.310106 |
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Cycle and phase accurate DSP modeling and integration for HW/SW co-verification |
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Lisa Guerra,
Joachim Fitzner,
Dipankar Talukdar,
Chris Schläger,
Bassam Tabbara,
Vojin Zivojnovic
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Pages: 964-969 |
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doi>10.1145/309847.310107 |
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A study in coverage-driven test generation |
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Mike Benjamin,
Daniel Geist,
Alan Hartman,
Gerard Mas,
Ralph Smeets,
Yaron Wolfsthal
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Pages: 970-975 |
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doi>10.1145/309847.310108 |
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IC test using the energy consumption ratio |
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Wanli Jiang,
Bapiraju Vinnakota
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Pages: 976-981 |
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doi>10.1145/309847.310109 |
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Design strategy of on-chip inductors for highly integrated RF systems |
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C. Patrick Yue,
S. Simon Wong
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Pages: 982-987 |
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doi>10.1145/309847.310110 |
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The simulation and design of integrated inductors |
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N. R. Belk,
M. R. Frei,
M. Tsai,
A. J. Becker,
K. L. Tokuda
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Pages: 988-993 |
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doi>10.1145/309847.310111 |
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Optimization of inductor circuits via geometric programming |
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Maria del Mar Hershenson,
Sunderarajan S. Mohan,
Stephen P. Boyd,
Thomas H. Lee
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Pages: 994-998 |
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doi>10.1145/309847.310112 |
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What is the proper system on chip design methodology (panel) |
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Richard Goering,
Pierre Bricaud,
James G. Dougherty,
Steve Glaser,
Michael Keating,
Robert Payne,
Davoud Samani
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Pages: 999-1000 |
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doi>10.1145/309847.310113 |
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