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Due to a patent dispute, full text of this article is not available at this time.
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Dennis Abts Dennis Abts

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Bibliometrics: publication history
Publication years1999-2014
Publication count21
Citation Count355
Available for download14
Downloads (6 Weeks)74
Downloads (12 Months)886
Downloads (cumulative)11,099
Average downloads per article792.79
Average citations per article16.90
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Author image not provided  Mike Roberts

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Bibliometrics: publication history
Publication years1999-2000
Publication count2
Citation Count3
Available for download1
Downloads (6 Weeks)0
Downloads (12 Months)2
Downloads (cumulative)137
Average downloads per article137.00
Average citations per article1.50
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top of pageREFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
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Asgeir Th. Eiraksson, John Keen, Alex Silbey, Swami Venkataraman, and Michael Woodacre, "Origin System Design Methodology and Experience: 1M-gate ASICs and Beyond," COMPCON-97.
 
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John Keen and Jon Michelson, "How to Use the KML Language," SGI Internal Report.
 
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"Spec-based Verification: A New Methodology for Functional Verification of Systems/ASICs," white paper, Verisity Design web page: www.verisity.com
 
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Mehdi Mohtashemi, "High-Performance Functional Validation," white paper, System Science Inc company web page: www. systems.com/products/vera/vera.htm
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"The Verilog-XL Reference Manual," Cadence Design Systems, 1991.
 
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K. Robbins and S. Robbins, "Practical UNIX Programming," Prentice Hall, 1996. p. 347-364.
 
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"Synopsys VCS Reference Manual," Synopsys, Inc., July, 1997.
 
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Summit Design, Inc. web page: http://www.sd.com

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The ACM Computing Classification System (CCS rev.2012)

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Title DAC '99 Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents
Editor Mary Jane Irwin
Pages 163-168
Publication Date1999-06-01 (yyyy-mm-dd)
Sponsors SIGDA ACM Special Interest Group on Design Automation
IEEE-CAS Circuits & Systems
EDAC Electronic Design Automation Consortium
PublisherACM New York, NY, USA ©1999
ISBN: 1-58113-109-7 doi>10.1145/309847.309907
Conference DACDesign Automation Conference DAC logo
Paper Acceptance Rate 154 of 451 submissions, 34%
Overall Acceptance Rate 3,150 of 10,963 submissions, 29%
Year Submitted Accepted Rate
DAC '84 290 116 40%
DAC '86 300 124 41%
DAC '87 351 138 39%
DAC '88 400 125 31%
DAC '89 465 156 34%
DAC '90 427 125 29%
DAC '94 260 100 38%
DAC '96 377 142 38%
DAC '97 400 139 35%
DAC '98 390 142 36%
DAC '99 451 154 34%
DAC '00 390 142 36%
DAC '01 410 160 39%
DAC '02 491 147 30%
DAC '03 628 152 24%
DAC '04 785 163 21%
DAC '05 735 154 21%
DAC '07 659 152 23%
DAC '08 639 147 23%
DAC '09 684 148 22%
DAC '11 690 156 23%
DAC '12 741 168 23%
Overall 10,963 3,150 29%

APPEARS IN
Hardware Design

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top of pageTable of Contents

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Table of Contents
An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect
Jing-Rebecca Li, Frank Wang, Jacob K. White
Pages: 1-6
doi>10.1145/309847.309848
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Error bounded Padé approximation via bilinear conformal transformation
Chung-Ping Chen, D. F. Wong
Pages: 7-12
doi>10.1145/309847.309850
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Model-reduction of nonlinear circuits using Krylov-space techniques
Pavan K. Gunupudi, Michel S. Nakhla
Pages: 13-16
doi>10.1145/309847.309854
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ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
Bernard N. Sheehan
Pages: 17-21
doi>10.1145/309847.309855
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Why is ATPG easy?
Mukul R. Prasad, Philip Chong, Kurt Keutzer
Pages: 22-28
doi>10.1145/309847.309857
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Using lower bounds during dynamic BDD minimization
Rolf Drechsler, Wolfgang Günther
Pages: 29-32
doi>10.1145/309847.309858
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Optimization-intensive watermarking techniques for decision problems
Gang Qu, Jennifer L. Wong, Miodrag Potkonjak
Pages: 33-36
doi>10.1145/309847.309860
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Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems
Ali Dasdan, Sandy S. Irani, Rajesh K. Gupta
Pages: 37-42
doi>10.1145/309847.309862
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IP-based design methodology
Daniel D. Gajski
Page: 43
doi>10.1145/309847.309864
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ipChinook: an integrated IP-based design framework for distributed embedded systems
Pai Chou, Ross Ortega, Ken Hines, Kurt Patridge, Gaetano Borriello
Pages: 44-49
doi>10.1145/309847.309865
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Virtual simulation of distributed IP-based designs
Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
Pages: 50-55
doi>10.1145/309847.309866
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Common-case computation: a high-level technique for power and performance optimization
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
Pages: 56-61
doi>10.1145/309847.309867
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Layout techniques supporting the use of dual supply voltages for cell-based designs
Chingwei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang
Pages: 62-67
doi>10.1145/309847.309872
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Gate-level design exploiting dual supply voltages for power-driven applications
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Bone Jone
Pages: 68-71
doi>10.1145/309847.309873
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Synthesis of low power CMOS VLSI circuits using dual supply voltages
Vijay Sundararajan, Keshab K. Parhi
Pages: 72-75
doi>10.1145/309847.309876
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HW and SW in embedded system design: loveboat, shipwreck, or ships passing in the night
Raul Camposano, Kurt Keutzer, Jerry Fiddler, Alberto Sangiovanni-Vincentelli, Jim Lansford
Pages: 76-77
doi>10.1145/309847.309877
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Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
Xiang-Dong Tan, C.-J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan
Pages: 78-83
doi>10.1145/309847.309880
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FAR-DS: full-plane AWE routing with driver sizing
Jiang Hu, Sachin S. Sapatnekar
Pages: 84-89
doi>10.1145/309847.309881
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Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation
Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
Pages: 90-95
doi>10.1145/309847.309882
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Simultaneous routing and buffer insertion with restrictions on buffer locations
Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
Pages: 96-99
doi>10.1145/309847.309885
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Crosstalk minimization using wire perturbations
Prashant Saxena, C. L. Liu
Pages: 100-103
doi>10.1145/309847.309887
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Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Erik Brunvand, Steven Nowick, Kenneth Yun
Pages: 104-109
doi>10.1145/309847.309889
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Automatic synthesis and optimization of partially specified asynchronous systems
Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Yakovlev
Pages: 110-115
doi>10.1145/309847.309891
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CAD directions for high performance asynchronous circuits
Ken Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
Pages: 116-121
doi>10.1145/309847.309893
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A low power hardware/software partitioning approach for core-based embedded systems
Jörg Henkel
Pages: 122-127
doi>10.1145/309847.309896
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Synthesis of low-overhead interfaces for power-efficient communication over wide buses
L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi
Pages: 128-133
doi>10.1145/309847.309898
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Power conscious fixed priority scheduling for hard real-time systems
Youngsoo Shin, Kiyoung Choi
Pages: 134-139
doi>10.1145/309847.309901
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Memory exploration for low power, embedded systems
Wen-Tsong Shiue, Chaitali Chakrabarti
Pages: 140-145
doi>10.1145/309847.309902
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Distributed application development with Inferno
Ravi Sharma
Pages: 146-150
doi>10.1145/309847.309904
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Embedded application design using a real-time OS
David Stepner, Nagarajan Rajan, David Hui
Pages: 151-156
doi>10.1145/309847.310566
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The Jini architecture: dynamic services in a flexible network
Ken Arnold
Pages: 157-162
doi>10.1145/309847.309906
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Verifying large-scale multiprocessors using an abstract verification environment
Dennis Abts, Mike Roberts
Pages: 163-168
doi>10.1145/309847.309907
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Due to a patent dispute, full text of this article is not available at this time.
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Functional verification of the equator MAP1000 microprocessor
Jian Shen, Jacob Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-chau Chu, Guanghui Hu
Pages: 169-174
doi>10.1145/309847.309908
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Micro architecture coverage directed generation of test programs
Shmuel Ur, Yaov Yadin
Pages: 175-180
doi>10.1145/309847.309909
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Verification of a microprocessor using real world applications
You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung
Pages: 181-184
doi>10.1145/309847.311478
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High-level test generation for design verification of pipelined microprocessors
David Van Campenhout, Trevor Mudge, John P. Hayes
Pages: 185-188
doi>10.1145/309847.309912
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Developing an architecture validation suite: application to the PowerPC architecture
Laurent Fournier, Anatoly Koyfman, Moshe Levinger
Pages: 189-194
doi>10.1145/309847.309911
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Passive reduced-order models for interconnect simulation and their computation via Krylov-subspace algorithms
Roland W. Freund
Pages: 195-200
doi>10.1145/309847.309913
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Model order-reduction of RC(L) interconnect including variational analysis
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
Pages: 201-206
doi>10.1145/309847.309914
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Robust rational function approximation algorithm for model generation
Carlos P. Coelho, Joel R. Phillips, L. Miguel Silveira
Pages: 207-212
doi>10.1145/309847.309915
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Behavioral network graph: unifying the domains of high-level and logic synthesis
Reinaldo A. Bergamaschi
Pages: 213-218
doi>10.1145/309847.309916
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Soft scheduling in high level synthesis
Jianwen Zhu, Daniel D. Gajski
Pages: 219-224
doi>10.1145/309847.309917
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Graph coloring algorithms for fast evaluation of Curtis decompositions
Marek Perkowski, Rahul Malvi, Stan Grygiel, Mike Burns, Alan Mishchenko
Pages: 225-230
doi>10.1145/309847.309918
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Maximizing performance by retiming and clock skew scheduling
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
Pages: 231-236
doi>10.1145/309847.309919
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A practical approach to multiple-class retiming
Klaus Eckl, Jean Christophe Madre, Peter Zepter, Christian Legl
Pages: 237-242
doi>10.1145/309847.309920
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Performance-driven integration of retiming and resynthesis
Peichen Pan
Pages: 243-246
doi>10.1145/309847.309921
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Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
L. Benini, G. De Micheli, E. Macii, G. Odasso, M. Poncino
Pages: 247-252
doi>10.1145/309847.309922
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Customized instruction-sets for embedded processors
Joseph A. Fisher
Pages: 253-257
doi>10.1145/309847.309923
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System-level hardware/software trade-offs
Samuel P. Harbison
Pages: 258-259
doi>10.1145/309847.309924
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Functional verification—real users, real problems, real opportunities (panel)
Nozar Azarakhsh, Glen Ewing, Paul Gingras, Scott Reedstrom, Chris Rowen / Jonah McLeod
Pages: 260-261
doi>10.1145/309847.309925
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A timing-driven soft-macro resynthesis method in interaction with chip floorplanning
Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
Pages: 262-267
doi>10.1145/309847.309926
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An O-tree representation of non-slicing floorplan and its applications
Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura
Pages: 268-273
doi>10.1145/309847.309928
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Module placement for analog layout using the sequence-pair representation
Florin Balasa, Koen Lampaert
Pages: 274-279
doi>10.1145/309847.309930
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Genetic list scheduling algorithm for scheduling and allocation on a loosely coupled heterogeneous multiprocessor system
Martin Grajcar
Pages: 280-285
doi>10.1145/309847.309931
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Performance-driven scheduling with bit-level chaining
Sanghun Park, Kiyoung Choi
Pages: 286-291
doi>10.1145/309847.309932
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A model for scheduling protocol-constrained components and environments
Steve Haynal, Forrest Brewer
Pages: 292-295
doi>10.1145/309847.309933
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A reordering technique for efficient code motion
Luiz C. V. dos Santos, Jochen A. G. Jess
Pages: 296-299
doi>10.1145/309847.309935
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Coverage estimation for symbolic model checking
Yatin Hoskote, Timothy Kam, Pei-Hsin Ho, Xudong Zhao
Pages: 300-305
doi>10.1145/309847.309936
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Improving symbolic traversals by means of activity profiles
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Pages: 306-311
doi>10.1145/309847.309938
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Improved approximate reachability using auxiliary state variables
Shankar G. Govindaraju, David L. Dill, Jules P. Bergmann
Pages: 312-316
doi>10.1145/309847.309940
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Symbolic model checking using SAT procedures instead of BDDs
A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, Y. Zhu
Pages: 317-320
doi>10.1145/309847.309942
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Power efficient mediaprocessors: design space exploration
Johnson Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak
Pages: 321-326
doi>10.1145/309847.309943
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Global multimedia system design exploration using accurate memory organization feedback
Arnout Vandecappelle, Miguel Miranda, Erik Brockmeyer, Francky Catthoor, Diederik Verkest
Pages: 327-332
doi>10.1145/309847.309945
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Implementation of a scalable MPEG-4 wavelet-based visual texture compression system
L. Nachtergaele, B. Vanhoof, M. Peón, G. Lafruit, J. Bormans, I. Bolsens
Pages: 333-336
doi>10.1145/309847.309948
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A 10 Mbit/s upstream cable modem with automatic equalization
Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels
Pages: 337-340
doi>10.1145/309847.309950
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Cell libraries—build vs. buy; static vs. dynamic (panel)
Kurt Wolf, David Pietromonaco, Jay Maxey, Jeff Lewis, Martin Lefebvre, Jeff Burns / Kurt Keutzer
Pages: 341-342
doi>10.1145/309847.309951
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Multilevel k-way hypergraph partitioning
George Karypis, Vipin Kumar
Pages: 343-348
doi>10.1145/309847.309954
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Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting
Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
Pages: 349-354
doi>10.1145/309847.309955
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Hypergraph partitioning with fixed vertices
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
Pages: 355-359
doi>10.1145/309847.309957
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Relaxation and clustering in a local search framework: application to linear placement
Sung-Woo Hur, John Lillis
Pages: 360-366
doi>10.1145/309847.309958
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An &agr;-approxmimate algorithm for delay-constraint technology mapping
Sumit Roy, Krishna Belkhale, Prithviraj Banerjee
Pages: 367-372
doi>10.1145/309847.309960
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Technology mapping for FPGAs with nonuniform pin delays and fast interconnections
Jason Cong, Yean-Yow Hwang, Songjie Xu
Pages: 373-378
doi>10.1145/309847.309963
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Automated phase assignment for the synthesis of low power domino circuits
Priyadarshan Patra, Unni Narayanan
Pages: 379-384
doi>10.1145/309847.309964
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Enhancing simulation with BDDs and ATPG
Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann
Pages: 385-390
doi>10.1145/309847.309965
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Cycle-based symbolic simulation of gate-level synchronous circuits
Valeria Bertacco, Maurizio Damiani, Stefano Quer
Pages: 391-396
doi>10.1145/309847.309966
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Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors
Miroslav N. Velev, Randal E. Bryant
Pages: 397-401
doi>10.1145/309847.309967
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Formal verification using parametric representations of Boolean constraints
Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Serger
Pages: 402-407
doi>10.1145/309847.309968
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Vertical benchmarks for CAD
Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass
Pages: 408-413
doi>10.1145/309847.309969
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A framework for user assisted design space exploration
X. Hu, G. W Greenwood, S. Ravichandran, G. Quan
Pages: 414-419
doi>10.1145/309847.309970
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Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design
Benoit Clement, Richard Hersemeule, Etienne Lantreibecq, Bernard Ramanadin, Pierre Coulomb, Francois Pogodalla
Pages: 420-424
doi>10.1145/309847.309971
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Verification and management of a multimillion-gate embedded core design
Johann Notbauer, Thomas Albrecht, Georg Niedrist, Stefan Rohringer
Pages: 425-428
doi>10.1145/309847.309972
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Parasitic extraction accuracy; how much is enough? (panel)
Mark Basel, Aki Fujimara, Sharad Mehrotra, Ron Preston, Robin C. Sarma, Marty Walker / Paul Franzon
Page: 429
doi>10.1145/309847.309973
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Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
Pages: 430-435
doi>10.1145/309847.309974
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Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw
Pages: 436-441
doi>10.1145/309847.309975
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Leakage control with efficient use of transistor stacks in single threshold CMOS
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
Pages: 442-445
doi>10.1145/309847.309976
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A practical gate resizing technique considering glitch reduction for low power design
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
Pages: 446-451
doi>10.1145/309847.309977
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Gradient-based optimization of custom circuits using a static-timing formulation
A. R. Conn, I. M. Elfadel, W. W. Molzen, Jr., P. R. O'Brien, P. N. Strenski, C. Visweswariah, C. B. Whan
Pages: 452-459
doi>10.1145/309847.309979
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Simultaneous circuit partitioning/clustering with retiming for performance optimization
Jason Cong, Honching Li, Chang Wu
Pages: 460-465
doi>10.1145/309847.309980
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Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long
Pages: 466-471
doi>10.1145/309847.309981
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MERLIN: semi-order-independent hierarchical buffered routing tree generation using local neighborhood search
Amir H. Salek, Jinan Lou, Massoud Pedram
Pages: 472-478
doi>10.1145/309847.309982
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Buffer insertion with accurate gate and interconnect delay computation
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
Pages: 479-484
doi>10.1145/309847.309983
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Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Joon-Seo Yim, Chong-Min Kyung
Pages: 485-490
doi>10.1145/309847.309984
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A novel VLSI layout fabric for deep sub-micron applications
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralf H. J. M. Otten, Alberto Sangiovanni-Vincentelli
Pages: 491-496
doi>10.1145/309847.309985
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Improved delay prediction for on-chip buses
Real G. Pomerleau, Paul D. Frazon, Griff L. Bilbro
Pages: 497-501
doi>10.1145/309847.309986
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Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching
Chung-Ping Chen, Noel Menezes
Pages: 502-506
doi>10.1145/309847.309987
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Interconnect estimation and planning for deep submicron designs
Jason Cong, David Zhigang Pan
Pages: 507-510
doi>10.1145/309847.309988
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ECL: a specification environment for system-level design
Luciano Lavagno, Ellen Sentovich
Pages: 511-516
doi>10.1145/309847.309989
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Representation of function variants for embedded system optimization and synthesis
K. Richter, D. Ziegenbein, R. Ernst, L. Thiele, J. Teich
Pages: 517-522
doi>10.1145/309847.309990
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Vex—A CAD toolbox
Jules P. Bergmann, Mark A. Horowitz
Pages: 523-528
doi>10.1145/309847.309991
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Constraint management for collaborative electronic design
Juan Antonio Carballo, Stephen W. Director
Pages: 529-534
doi>10.1145/309847.309992
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MEMS CAD beyond multi-million transistors (panel)
Albert P. Pisano, Nicholas Swart, Mike Horton, John Rychcik, John R. Gilbert, Gerry K. Fedder / Kris Pister
Pages: 535-536
doi>10.1145/309847.309993
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A multiscale method for fast capacitance extraction
Johannes Tausch, Jacob White
Pages: 537-542
doi>10.1145/309847.309994
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Efficient capacitance computation for structures with non-uniform adaptive surface meshes
Vikram Jandhyala, Scott Savage, Eric Bracken, Zoltan Cendes
Pages: 543-548
doi>10.1145/309847.309995
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Substrate modeling and lumped substrate resistance extraction for CMOS ESD/latchup circuit simulation
Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang
Pages: 549-554
doi>10.1145/309847.309996
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Dynamic power management based on continuous-time Markov decision processes
Qinru Qiu, Massoud Pedram
Pages: 555-561
doi>10.1145/309847.309997
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Parallel mixed-level power simulation based on spatio-temporal circuit partitioning
Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
Pages: 562-567
doi>10.1145/309847.309998
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Low-power behavioral synthesis optimization using multiple precision arithmetic
Milos Ercegovac, Darko Kirovski, Miodrag Potkonjak
Pages: 568-573
doi>10.1145/309847.310000
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A methodology for the verification of a “system on chip”
Daniel Geist, Giora Biran, Tamara Arons, Michael Slavkin, Yvgeny Nustov, Monica Farkas, Karen Holtz, Andy Long, Dave King, Steve Barret
Pages: 574-579
doi>10.1145/309847.310001
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ICEBERG: an embedded in-circuit emulator synthesizer for microcontrollers
Ing-Jer Huang, Tai-An Lu
Pages: 580-585
doi>10.1145/309847.310003
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Microprocessor based testing for core-based system on chip
C. A. Papachristou, F. Martin, M. Nourani
Pages: 586-591
doi>10.1145/309847.310004
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Using partitioning to help convergence in the standard-cell design automation methodology
Hema Kapadia, Mark Horowitz
Pages: 592-597
doi>10.1145/309847.310005
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Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper
Imed Moussa, Zoltan Sugar, Rodolph Suescun, Mario Diaz-Nava, Marco Pavesi, Salvatore Crudo, Luca Gazi, Ahmed Amine Jerraya
Pages: 598-603
doi>10.1145/309847.310006
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Engineering change: methodology and applications to behavioral and system synthesis
Darko Kirovski, Miodrag Potkonjak
Pages: 604-609
doi>10.1145/309847.310007
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Reconfigurable computing: what, why, and implications for design automation
André DeHon, John Wawrzynek
Pages: 610-615
doi>10.1145/309847.310009
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An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications
Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss
Pages: 616-622
doi>10.1145/309847.310010
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Dynamically reconfigurable architecture for image processor applications
Alexandro M. S. Adário, Eduardo L. Roehe, Sergio Bampi
Pages: 623-628
doi>10.1145/309847.310012
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Multi-time simulation of voltage-controlled oscillators
Onuttom Narayan, Jaijeet Roychowdhury
Pages: 629-634
doi>10.1145/309847.310014
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Efficient computation of quasi-periodic circuit operating conditions via a mixed frequency/time approach
Dan Feng, Joel Phillips, Keith Nabors, Ken Kundert, Jacob White
Pages: 635-640
doi>10.1145/309847.310015
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Time-mapped harmonic balance
Ognen J. Nastov, Jacob K. White
Pages: 641-646
doi>10.1145/309847.310016
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Test generation for Gigahertz processors using an automatic functional constraint extractor
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham
Pages: 647-652
doi>10.1145/309847.310018
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Proptest: a property based test pattern generator for sequential circuits using test compaction
Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
Pages: 653-659
doi>10.1145/309847.310019
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Multiple error diagnosis based on xlists
Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
Pages: 660-665
doi>10.1145/309847.310021
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Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Farzan Fallah, Pranav Ashar, Srinivas Devadas
Pages: 666-671
doi>10.1145/309847.310023
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A two-state methodology for RTL logic simulation
Lionel Bening
Pages: 672-677
doi>10.1145/309847.310024
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An approach for extracting RT timing information to annotate algorithmic VHDL specifications
Cordula Hansen, Francisco Nascimento, Wolfgang Rosenstiel
Pages: 678-683
doi>10.1145/309847.310026
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A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Miron Abramovici, Jose T. de Sousa, Daniel Saab
Pages: 684-690
doi>10.1145/309847.310028
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Dynamic fault diagnosis on reconfigurable hardware
Fatih Kocan, Daniel G. Saab
Pages: 691-696
doi>10.1145/309847.310029
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Hardware compilation for FPGA-based configurable computing machines
Xiaohan Zhu, Bill Lin
Pages: 697-702
doi>10.1145/309847.310030
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0.18μm CMOS and beyond
D. J. Eaglesham
Pages: 703-708
doi>10.1145/309847.310032
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SOI digital CMOS VLSI—a design perspective
C. T. Chuang, R. Puri
Pages: 709-714
doi>10.1145/309847.310034
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Equivalent Elmore delay for RLC trees
Yehea I. Ismail, Eby G. Friedman, Jose L. Neves
Pages: 715-720
doi>10.1145/309847.310041
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Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Yehea I. Ismail, Eby G. Friedman
Pages: 721-724
doi>10.1145/309847.310042
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Retiming for DSM with area-delay trade-offs and delay constraints
Abdallah Tabbara, Robert K. Brayton, A. Richard Newton
Pages: 725-730
doi>10.1145/309847.310044
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Functional timing analysis for IP characterization
Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem Sakallah
Pages: 731-736
doi>10.1145/309847.310045
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Detecting false timing paths: experiments on PowerPC microprocessors
Richard Raimi, Jacob Abraham
Pages: 737-741
doi>10.1145/309847.310047
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On ILP formulations for built-in self-testable data path synthesis
Han Bin Kim, Dong Sam Ha, Takeshi Takahashi
Pages: 742-747
doi>10.1145/309847.310048
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Improving the test quality for scan-based BIST using a general test application scheme
Huan-Chih Tsai, Kwang-Tin Cheng, Sudipta Bhawmik
Pages: 748-753
doi>10.1145/309847.310050
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Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences
Irith Pomeranz, Sudhakar M. Reddy
Pages: 754-759
doi>10.1145/309847.310052
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Analysis of performance impact caused by power supply noise in deep submicron devices
Yi-Min Jiang, Kwang-Ting Cheng
Pages: 760-765
doi>10.1145/309847.310053
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A floorplan-based planning methodology for power and clock distribution in ASICs
Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung
Pages: 766-771
doi>10.1145/309847.310054
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Digital detection of analog parametric faults in SC filters
Ramesh Harjani, Bapiraju Vinnakota
Pages: 772-777
doi>10.1145/309847.310056
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Application of high level interface-based design to telecommunications system hardware
Dyson Wilkes, M. M. Kamal Hashmi
Pages: 778-783
doi>10.1145/309847.310057
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Hardware reuse at the behavioral level
Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels, Ivo Bolsens
Pages: 784-789
doi>10.1145/309847.310058
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Description and simulation of hardware/software systems with Java
Tommy Kuhn, Wolfgang Rosenstiel, Udo Kebschull
Pages: 790-793
doi>10.1145/309847.310059
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Java driven codesign and prototyping of networked embedded systems
Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
Pages: 794-797
doi>10.1145/309847.310068
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Subwavelength lithography (panel): how will it affect your design flow?
Y. C. Pati, Warren Grobman, Robert Pack, Lance Glasser / Andrew B. Kahng
Page: 798
doi>10.1145/309847.310070
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Subwavelength lithography and its potential impact on design and EDA
Andrew B. Kahng, Y. C. Pati
Pages: 799-804
doi>10.1145/309847.310072
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Synthesis of embedded software using free-choice Petri nets
Marco Sgroi, Luciano Lavagno, Yosinori Watanabe, Alberto Sangiovanni-Vincentelli
Pages: 805-810
doi>10.1145/309847.310073
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Exact memory size estimation for array computations without loop unrolling
Ying Zhao, Sharad Malik
Pages: 811-816
doi>10.1145/309847.310074
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Constraint driven code selection for fixed-point DSPs
Steven Bashford, Rainer Leupers
Pages: 817-822
doi>10.1145/309847.310076
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Rapid development of optimized DSP code from a high level description through software estimations
Alain Pegatoquet, Emmanuel Gresset, Michel Auguin, Luc Bianco
Pages: 823-826
doi>10.1145/309847.310077
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Software environment for a multiprocessor DSP
Asawaree Kalavade, Joe Othmer, Bryan Ackland, K. J. Singh
Pages: 827-830
doi>10.1145/309847.310078
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Robust FPGA intellectual property protection through multiple small watermarks
John Lach, William H. Mangione-Smith, Miodrag Potkonjak
Pages: 831-836
doi>10.1145/309847.310080
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Robust techniques for watermarking sequential circuit designs
Arlindo L. Oliveira
Pages: 837-842
doi>10.1145/309847.310082
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Effective iterative techniques for fingerprinting design IP
Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
Pages: 843-848
doi>10.1145/309847.310083
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Behavioral synthesis techniques for intellectual property protection
Inki Hong, Miodrag Potkonjak
Pages: 849-854
doi>10.1145/309847.310085
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Design and implementation of a scalable encryption processor with embedded variable DC/DC converter
James Goodman, Anantha Chandrakasan, Abram P. Dancy
Pages: 855-860
doi>10.1145/309847.310087
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Design considerations for battery-powered electronics
Massoud Pedram, Qing Wu
Pages: 861-866
doi>10.1145/309847.310089
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Cycle-accurate simulation of energy consumption in embedded systems
Tajana Šimunić, Luca Benini, Giovanni De Micheli
Pages: 867-872
doi>10.1145/309847.310090
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Lowering power consumption in clock by using globally asynchronous locally synchronous design style
A. Hemani, T. Meincke, S. Kumar, A. Postula, T. Olsson, P. Nilsson, J. Oberg, P. Ellervee, D. Lundqvist
Pages: 873-878
doi>10.1145/309847.310091
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A CAD tool for optical MEMS
Timothy P. Kurzweg, Steven P. Levitan, Philippe J. Marchand, Jose A. Martinez, Kurt R. Prough, Donald M. Chiarulli
Pages: 879-884
doi>10.1145/309847.310092
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On thermal effects in deep sub-micron VLSI interconnects
Kaustav Banerjee, Amit Mehrotra, Alberto Sangiovanni-Vincentelli, Chenming Hu
Pages: 885-891
doi>10.1145/309847.310093
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Converting a 64b PowerPC processor from CMOS bulk to SOI technology
D. Allen, D. Behrends, B. Stanisic
Pages: 892-897
doi>10.1145/309847.310094
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A framework for collaborative and distributed web-based design
Gangadhar Konduri, Anantha Chandrakasan
Pages: 898-903
doi>10.1145/309847.310095
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Dealing with inductance in high-speed chip design
Phillip Restle, Albert Ruehli, Steven G. Walker
Pages: 904-909
doi>10.1145/309847.310096
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Interconnect analysis: from 3-D structures to circuit models
M. Kamon, N. Marques, Y. Massoud, L. Silveira, J. White
Pages: 910-914
doi>10.1145/309847.310097
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IC analyses including extracted inductance models
Michael W. Beattie, Lawrence T. Pileggi
Pages: 915-920
doi>10.1145/309847.310098
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On-chip inductance issues in multiconductor systems
Shannon V. Morton
Pages: 921-926
doi>10.1145/309847.310099
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A methodology for accurate performance evaluation in architecture exploration
George Hadjiyiannis, Pietro Russo, Srinivas Devadas
Pages: 927-932
doi>10.1145/309847.310100
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LISA—machine description language for cycle-accurate models of programmable DSP architectures
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr
Pages: 933-938
doi>10.1145/309847.310101
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Exploiting intellectual properties in ASIP designs for embedded DSP software
Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung
Pages: 939-944
doi>10.1145/309847.310103
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MAELSTROM: efficient simulation-based synthesis for custom analog cells
Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley
Pages: 945-950
doi>10.1145/309847.310104
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Behavioral synthesis of analog systems using two-layered design space exploration
Alex Doboli, Adrian Nunez-Aldana, Nagu Dhanwada, Sree Ganesan, Ranga Vemuri
Pages: 951-957
doi>10.1145/309847.310105
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Circuit complexity reduction for symbolic analysis of analog integrated circuits
Walter Daems, Georges Gielen, Willy Sansen
Pages: 958-963
doi>10.1145/309847.310106
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Cycle and phase accurate DSP modeling and integration for HW/SW co-verification
Lisa Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schläger, Bassam Tabbara, Vojin Zivojnovic
Pages: 964-969
doi>10.1145/309847.310107
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A study in coverage-driven test generation
Mike Benjamin, Daniel Geist, Alan Hartman, Gerard Mas, Ralph Smeets, Yaron Wolfsthal
Pages: 970-975
doi>10.1145/309847.310108
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IC test using the energy consumption ratio
Wanli Jiang, Bapiraju Vinnakota
Pages: 976-981
doi>10.1145/309847.310109
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Design strategy of on-chip inductors for highly integrated RF systems
C. Patrick Yue, S. Simon Wong
Pages: 982-987
doi>10.1145/309847.310110
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The simulation and design of integrated inductors
N. R. Belk, M. R. Frei, M. Tsai, A. J. Becker, K. L. Tokuda
Pages: 988-993
doi>10.1145/309847.310111
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Optimization of inductor circuits via geometric programming
Maria del Mar Hershenson, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee
Pages: 994-998
doi>10.1145/309847.310112
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What is the proper system on chip design methodology (panel)
Richard Goering, Pierre Bricaud, James G. Dougherty, Steve Glaser, Michael Keating, Robert Payne, Davoud Samani
Pages: 999-1000
doi>10.1145/309847.310113
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