Symbolic model checking using SAT procedures instead of BDDs

doi:10.1145/309847.309942

Symbolic model checking using SAT procedures instead of BDDs

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Authors:	A. Biere	Computer Science Department, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA and Verysys Design Automation, Inc., 42707 Lawrence Place, Fremont, CA
	A. Cimatti	Istituto per la Ricerca Scientifica e Tecnolgica (IRST), via Sommarive 18, 38055 Povo (TN), Italy
	E. M. Clarke	Computer Science Department, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA and Verysys Design Automation, Inc., 42707 Lawrence Place, Fremont, CA
	M. Fujita	Fujitsu Laboratories of America, Inc., 595 Lawrence Expressway, Sunnyvale, CA
	Y. Zhu	Computer Science Department, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA and Verysys Design Automation, Inc., 42707 Lawrence Place, Fremont, CA

	1999 Article
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	· Proceeding
	DAC '99 Proceedings of the 36th annual ACM/IEEE Design Automation Conference
	Pages 317-320 ACM New York, NY, USA ©1999 table of contents ISBN:1-58113-109-7 doi>10.1145/309847.309942

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