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Improved delay prediction for on-chip buses
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Authors:
Real G. Pomerleau
North Carolina State University, CACC Box 7914, Raleigh, NC
Paul D. Frazon
North Carolina State University, CACC Box 7914, Raleigh, NC
Griff L. Bilbro
North Carolina State University, CACC Box 7914, Raleigh, NC
Published in:
· Proceeding
DAC '99
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Pages 497-501
ACM
New York, NY
, USA
©1999
table of contents
ISBN:1-58113-109-7
doi>
10.1145/309847.309986
1999 Article
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Tags:
buffer optimization
design
floorplanning
high-level synthesis
interconnect optimization
interconnections
measurement
optimization
performance
rc wiring delay
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