A methodology for the verification of a “system on chip”

doi:10.1145/309847.310001

A methodology for the verification of a “system on chip”

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Authors:	Daniel Geist	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
	Giora Biran	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
	Tamara Arons	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
	Michael Slavkin	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
	Yvgeny Nustov	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
	Monica Farkas	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
	Karen Holtz	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
	Andy Long	IBM Field Design Center, Essex Junction, VT
	Dave King	IBM Field Design Center, Essex Junction, VT
	Steve Barret	IBM Field Design Center, Essex Junction, VT

	1999 Article
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	· Proceeding
	DAC '99 Proceedings of the 36th annual ACM/IEEE Design Automation Conference
	Pages 574-579 ACM New York, NY, USA ©1999 table of contents ISBN:1-58113-109-7 doi>10.1145/309847.310001

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Tags: design reliability, testing, and fault-tolerance systems on chip test and debugging theory verification verification

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