Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

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Authors: Kanad Ghose Department of Computer Science, State University of New York, Binghamton, NY
Milind B. Kamble Hewlett-Packard VLSI Technology Labratory, Fort Collins, CO and Department of Computer Science, State University of New York, Binghamton, NY
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· Proceeding
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Pages 70-75
ACM New York, NY, USA ©1999
table of contents ISBN:1-58113-133-X doi>10.1145/313817.313860
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation Published by ACM 1999 Article
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