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A unified approach to simulation and timing verification at the functional level

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Authors: Vighneswara Row Mokkarala Hewlett Packard Co., 11000 Wolfe Road, Cupertino, California
Antony Fan Valid Logic Systems, Inc. and Hewlett Packard Co., 11000 Wolfe Road, Cupertino, California
Ravi Apte Valid Logic Systems, Inc. and Hewlett Packard Co., 11000 Wolfe Road, Cupertino, California
Published in:
· Proceeding
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
ACM New York, NY, USA ©1985
table of contents ISBN:0-8186-0635-5 doi>10.1145/317825.317981
A unified approach to simulation and timing verification at the functional level Published by ACM 1985 Article
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