A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance

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Authors: Vikas Mehrotra Massachusetts Institute of Technology, Cambridge, MA
Shiou Lin Sam Massachusetts Institute of Technology, Cambridge, MA
Duane Boning Massachusetts Institute of Technology, Cambridge, MA
Anantha Chandrakasan Massachusetts Institute of Technology, Cambridge, MA
Rakesh Vallishayee PDF Solutions, San Jose, CA
Sani Nassif IBM, Austin, TX
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance Published by ACM 2000 Article
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· Proceeding
DAC '00 Proceedings of the 37th Annual Design Automation Conference
Pages 172-175
ACM New York, NY, USA ©2000
table of contents ISBN:1-58113-187-9 doi>10.1145/337292.337370

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