“Timing closure by design,” a high frequency microprocessor design methodology

doi:10.1145/337292.337749

“Timing closure by design,” a high frequency microprocessor design methodology

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Authors:	S. Posluszny	IBM Austin Research Lab, Austin, TX
	N. Aoki	IBM Austin Research Lab, Austin, TX
	D. Boerstler	IBM Austin Research Lab, Austin, TX
	P. Coulman	IBM Server Division, Austin, TX
	S. Dhong	IBM Austin Research Lab, Austin, TX
	B. Flachs	Motorola, Austin, TX
	P. Hofstee	IBM Austin Research Lab, Austin, TX
	N. Kojima	IBM Austin Research Lab, Austin, TX
	O. Kwon	IBM Austin Research Lab, Austin, TX
	K. Lee	Sun Microsystems, CA
	D. Meltzer	IBM Watson Research Lab, Yorktown, NY
	K. Nowka	IBM Austin Research Lab, Austin, TX
	J. Park	Samsung, Korea
	J. Peter	IBM Austin Research Lab, Austin, TX
	J. Silberman	IBM Watson Research Lab, Yorktown, NY
	O. Takahashi	IBM Austin Research Lab, Austin, TX
	P. Villarrubia	IBM Server Division, Austin, TX

	2000 Article
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	· Proceeding
	DAC '00 Proceedings of the 37th Annual Design Automation Conference
	Pages 712-717 ACM New York, NY, USA ©2000 table of contents ISBN:1-58113-187-9 doi>10.1145/337292.337749

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Tags: cad chip integration design dynamic circuits0 logic arrays methodology microprocessor performance pla placement and routing routing and layout theory timing analysis timing closure

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