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An empirical study on how program layout affects cache miss rates
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Authors:
Jeffrey P. Bradford
Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Russell Quong
Sun Microsystems - SUN 03-201, 430 N Mary, Sunnyvale, CA
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· Newsletter
ACM SIGMETRICS Performance Evaluation Review
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Volume 27 Issue 3, Dec. 1999
Pages 28-42
ACM
New York, NY
, USA
table of contents
doi>
10.1145/340242.340326
1999 Article
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Tags:
benchmarks
cache memories
design
experimentation
measurement
performance
routing and layout
standardization
theory
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