SIGN IN
SIGN UP
Further improve circuit partitioning using GBAW logic perturbation techniques
Full Text:
PDF
Buy this Article
Authors:
C. Cheung
The Chinese University of HK, Shatin, NT, Hong Kong
Y. Wu
The Chinese University of HK, Shatin, NT, Hong Kong
D. Cheng
Ultima Interconnect Technology, Sunnyvale, CA
Published in:
· Proceeding
DATE '01
Proceedings of the conference on Design, automation and test in Europe
IEEE Press
Piscataway, NJ
, USA
©2001
table of contents
ISBN:0-7695-0993-2
2001 Article
Bibliometrics
· Downloads (6 Weeks): 1
· Downloads (12 Months): 5
· Citation Count: 1
Tools and Resources
Buy this Article
TOC Service:
Email
RSS
Save to Binder
Export Formats:
BibTeX
EndNote
ACM Ref
Share:
|
Tags:
algorithms
algorithms implemented in hardware
design
layout
performance
sequential circuits
Feedback
|
Switch to
single page view
(no tabs)
**Javascript is not enabled and is required for the "tabbed view" or switch to the
single page view
**
Powered by
The ACM Guide to Computing Literature
All Tags
Export Formats
Save to Binder