Full chip false timing path identification: applications to the PowerPCTM microprocessors

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Authors:	J. Zeng	EDA Tools and Methodology, Motorola ASP Somerset Design Center, Austin, TX and Computer Engineering Research Center, The University of Texas at Austin, Austin, TX
	M. Abadir	EDA Tools and Methodology, Motorola ASP Somerset Design Center, Austin, TX
	J. Bhadra	EDA Tools and Methodology, Motorola ASP Somerset Design Center, Austin, TX and Computer Engineering Research Center, The University of Texas at Austin, Austin, TX
	J. Abraham	Computer Engineering Research Center, The University of Texas at Austin, Austin, TX