A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits

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Authors: O. Garnica Universidad Complutense de Madrid, Dpto. Arquitectura de Computadores
J. Lanchares Universidad Complutense de Madrid, Dpto. Arquitectura de Computadores
R. Hermida Universidad Complutense de Madrid, Dpto. Arquitectura de Computadores
Published in:
· Proceeding
DATE '01 Proceedings of the conference on Design, automation and test in Europe
Page 810
IEEE Press Piscataway, NJ, USA ©2001
table of contents ISBN:0-7695-0993-2
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits 2001 Article
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