Layout generation of array cell for NMOS 4-phase dynamic logic (short paper)

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Authors:	Makoto Furuie	Dept. of Information Systems Engineering, Osaka University, Suita, Osaka, 565-0871, Japan
	Bao-Yu Song	Dept. of Information Systems Engineering, Osaka University, Suita, Osaka, 565-0871, Japan
	Yukihiro Yoshida	Dept. of Information Systems Engineering, Osaka University, Suita, Osaka, 565-0871, Japan
	Takao Onoye	Dept. of Communications and Computer Engineering, Kyoto University, Kyoto, Kyoto, 606-8501, Japan
	Isao Shirakawa	Dept. of Information Systems Engineering, Osaka University, Suita, Osaka, 565-0871, Japan