Clock design of 300MHz 128-bit 2-way superscalar microprocessor

Full Text: PDFPDF Buy this ArticleBuy this Article
Authors: Fujio Ishihara Processor Development Group, System ULSI Eng. Lab., Microelec. Eng. Lab., TOSHIBA CORPORATION, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan
Christian Klinger TOSHIBA AMERICA, ELEC. COMPONENTS, INC., 1060 Rincon Circle, San Jose, California
Ken-ichi Agawa Mobile and Network Development. Group, System ULSI Eng. Lab., Microelectronics Engineering Lab., TOSHIBA CORPORATION, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210-8520, Japan
Published in:
· Proceeding
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Pages 647-652
ACM New York, NY, USA ©2000
table of contents ISBN:0-7803-5974-7 doi>10.1145/368434.368857
Clock design of 300MHz 128-bit 2-way superscalar microprocessor Published by ACM 2000 Article
Bibliometrics Data  Bibliometrics
· Downloads (6 Weeks): 1
· Downloads (12 Months): 5
· Downloads (cumulative): 144
· Citation Count: 3


Tools and Resources

Share:

|
feedback Feedback | Switch to single page view (no tabs)

Powered by The ACM Guide to Computing Literature


The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2013 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player
The ACM Guide to Computing Literature
All Tags
Export Formats
 
 
Save to Binder