Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

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Authors: Randal E. Bryant Carnegie Mellon Univ., Pittsburgh, PA
Steven German IBM Watson Research Center, Yorktown Heights, NY
Miroslav N. Velev Carnegie Mellon Univ., Pittsburgh, PA
Published in:
· Journal
ACM Transactions on Computational Logic (TOCL) TOCL Homepage archive
Volume 2 Issue 1, Jan. 2001
Pages 93 - 134
ACM New York, NY, USA
table of contents doi>10.1145/371282.371364
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic Published by ACM 2001 Article
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