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Data and memory optimization techniques for embedded systems
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Authors:
P. R. Panda
Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA
F. Catthoor
Inter-University Microelectronics Centre and Katholieke Universiteit Leuven, Kapeldreef 75, Leuven, Belgium
N. D. Dutt
Center for Embedded Computer Systems, University of California at Irvine, Irvine, CA
K. Danckaert
Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium
E. Brockmeyer
Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium
C. Kulkarni
Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium
A. Vandercappelle
Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium
P. G. Kjeldsberg
Norwegian University of Science and Technology, Trondheim, Norway
2001 Article
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· Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TODAES Homepage
archive
Volume 6 Issue 2, April 2001
Pages 149 - 206
ACM
New York, NY
, USA
table of contents
doi>
10.1145/375977.375978
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Tags:
address generation
algorithms
allocation
architecture exploration
code transformation
data cache
data optimization
design
dram
experimentation
general
high-level synthesis
memory architecture customization
memory design
memory power dissipation
memory technologies
optimization
performance
register file
size estimation
sram
survey
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